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Hazar Yueksel
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2020 – today
- 2020
- [j3]Gain Kim, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg
, Thomas Toifl, Yusuf Leblebici, Lukas Kull, Danny Luu, Matthias Braendli
, Christian Menolfi, Pier Andrea Francese
, Hazar Yueksel, Cosimo Aprile, Thomas Morf:
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET. IEEE J. Solid State Circuits 55(1): 38-48 (2020) - [c16]Sanghamitra Dutta, Dennis Wei, Hazar Yueksel, Pin-Yu Chen, Sijia Liu, Kush R. Varshney:
Is There a Trade-Off Between Fairness and Accuracy? A Perspective Using Mismatched Hypothesis Testing. ICML 2020: 2803-2813
2010 – 2019
- 2019
- [c15]Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli
, Christian Menolfi, Pier Andrea Francese
, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Hyeon-Min Bae, Andreas Burg
, Thomas Toifl, Yusuf Leblebici:
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. A-SSCC 2019: 239-240 - [c14]Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli
, Christian Menolfi, Pier Andrea Francese
, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg
, Thomas Toifl, Yusuf Leblebici:
A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET. ISSCC 2019: 476-478 - [i1]Sanghamitra Dutta, Dennis Wei, Hazar Yueksel, Pin-Yu Chen, Sijia Liu, Kush R. Varshney:
An Information-Theoretic Perspective on the Relationship Between Fairness and Accuracy. CoRR abs/1910.07870 (2019) - 2018
- [j2]Danny Luu, Lukas Kull, Thomas Toifl, Christian Menolfi, Matthias Braendli
, Pier Andrea Francese
, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Qiuting Huang:
A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 53(11): 3268-3279 (2018) - [j1]Hazar Yueksel, Matthias Braendli
, Andreas Burg
, Giovanni Cherubini
, Roy D. Cideciyan, Pier Andrea Francese
, Simeon Furrer, Marcel A. Kossel, Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Thomas Toifl:
Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3529-3542 (2018) - 2017
- [c13]Marcel A. Kossel, Christian Menolfi, Pier Andrea Francese
, Lukas Kull, Thomas Morf, Thomas Toifl, Matthias Braendli
, Alessandro Cevrero, Danny Luu, Ilter Özkaya, Hazar Yueksel:
DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology. ESSCIRC 2017: 115-118 - [c12]Danny Luu, Lukas Kull, Thomas Toifl, Christian Menolfi, Matthias Braendli
, Pier Andrea Francese
, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Qiuting Huang:
Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET. ESSCIRC 2017: 183-186 - [c11]Lukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli
, Pier Andrea Francese
, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl:
28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET. ISSCC 2017: 474-475 - 2016
- [c10]Hazar Yueksel, Giovanni Cherubini, Roy D. Cideciyan, Simeon Furrer, Andreas Burg
, Thomas Toifl:
High-speed link with trellis-coded modulation and Reed-Solomon coding. CSCN 2016: 231-236 - [c9]Hazar Yueksel, Matthias Braendli
, Andreas Burg
, Giovanni Cherubini, Roy D. Cideciyan, Pier Andrea Francese
, Simeon Furrer, Marcel A. Kossel, Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Thomas Toifl:
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS. ESSCIRC 2016: 309-312 - [c8]Thomas Toifl, Matthias Braendli
, Alessandro Cevrero, Pier Andrea Francese
, Marcel A. Kossel, Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Ilter Özkaya, Hazar Yueksel:
Design considerations for 50G+ backplane links. ESSCIRC 2016: 477-482 - [c7]Hazar Yueksel, Giovanni Cherubini, Roy D. Cideciyan, Andreas Burg
, Thomas Toifl:
Design considerations on sliding-block viterbi detectors for high-speed data transmission. ICSPCS 2016: 1-6 - [c6]Pier Andrea Francese
, Matthias Braendli
, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Alessandro Cevrero, Hazar Yueksel, Ilter Oezkaya, Danny Luu, Thomas Toifl:
23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path. ISSCC 2016: 408-409 - 2015
- [c5]Hazar Yueksel, Lukas Kull, Andreas Burg
, Matthias Braendli
, Peter Buchmann, Pier Andrea Francese
, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Danny Luu, Thomas Toifl:
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS. ESSCIRC 2015: 148-151 - [c4]Pier Andrea Francese
, Thomas Toifl, Matthias Braendli
, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel, Alessandro Cevrero, Danny Luu:
10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver. ISSCC 2015: 1-3 - [c3]Alessandro Cevrero, Cosimo Aprile, Pier Andrea Francese
, U. Bapst, Christian Menolfi, Matthias Braendli
, Marcel A. Kossel, Thomas Morf, Lukas Kull, Hazar Yueksel, Ilter Oezkaya, Yusuf Leblebici, Volkan Cevher
, Thomas Toifl:
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS. VLSIC 2015: 228- - 2014
- [c2]Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese
, Matthias Braendli
, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel:
A DDR3/4 memory link TX supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI. ESSCIRC 2014: 135-138 - [c1]Pier Andrea Francese
, Thomas Toifl, Matthias Braendli
, Peter Buchmann, Thomas Morf, Marcel A. Kossel, Christian Menolfi, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel:
A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS. ESSCIRC 2014: 435-438
Coauthor Index
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last updated on 2024-05-08 20:55 CEST by the dblp team
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