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2020 – today
- 2023
[j3]Wenwu Xiao, Yue Peng, Yan Liu, Huifu Duan, Fujun Bai, Bing Yu, Qiwei Ren, Xiao Yu, Genquan Han:
Hf0.5Zr0.5O2 1T-1C FeRAM arrays with excellent endurance performance for embedded memory. Sci. China Inf. Sci. 66(4) (2023)- [j2]Fujun Bai
, Song Wang, Xuerong Jia, Yixin Guo, Bing Yu, Hang Wang, Cong Lai, Qiwei Ren, Hongbin Sun:
A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder. IEEE Trans. Very Large Scale Integr. Syst. 31(1): 128-141 (2023) - [c6]Qiwei Ren, Qiyishu Li, Zhikun Xu, Zhengang Pan:
Low Overhead Pilot Design for Channel Estimation in MIMO-OTFS Systems. ICCC Workshops 2023: 1-6 - [c5]Song Wang, Bing Yu, Wenwu Xiao, Fujun Bai, Xiaodong Long, Liang Bai, Xuerong Jia, Fengguo Zuo, Jie Tan, Yixin Guo, Peng Sun, Jun Zhou, Qiong Zhan, Sheng Hu, Yu Zhou, Yi Kang, Qiwei Ren, Xiping Jiang:
A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c4]Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie:
184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System. ISSCC 2022: 1-3 - 2021
- [c3]Xiping Jiang, Fengguo Zuo, Song Wang, Xiaofeng Zhou, Bing Yu, Yubing Wang, Qi Liu, Ming Liu, Yi Kang, Qiwei Ren:
A 1596GB/s 48Gb Embedded DRAM 384-Core SoC with Hybrid Bonding Integration. A-SSCC 2021: 1-3
2010 – 2019
- 2017
- [c2]Fujun Bai, Baoyu Xiong, Xiaofei Xue, Weizhe Song, Baofeng Wu, Ni Fu, Bing Yu, Huifu Duan, Xiaowei Han, Alessandro Minzoni, Qiwei Ren:
A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area & 63% standby power. ASICON 2017: 426-428 - [c1]Xiaowei Han, Qian Jia, Hongbin Sun, Longfei Wang, Huaqiang Wu, Yimao Cai, Feng Zhang, Yongyi Xie, Fangxu Dong, Xiaoguang Wang, Xiaofei Xue, Li Pang, Xiaoqing Zhao, Mengnan Wu, Pu Bai, Qi Liu, Hangbing Lv, Bing Yu, Chao Zhao, He Qian, Ru Huang, Ming Liu, Yumei Zhou, Nanning Zheng, Qiwei Ren:
A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement. CICC 2017: 1-4 - 2015
- [j1]Minjie Lv, Hongbin Sun, Qiwei Ren, Bing Yu, Jingmin Xin, Nanning Zheng:
Logic-DRAM Co-Design to Exploit the Efficient Repair Technique for Stacked DRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1362-1371 (2015)
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