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Hiroshi Miyanaga

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1990 – 1999

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1991
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Hiroshi Miyanaga, Hironori Yamauchi, Kazuhiro Matsuda:
A real-time 256×256 point two-dimensional FFT single-chip processor. ICASSP 1991: 1193-1196

1980 – 1989

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1987
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Naoaki Yamanaka, Hiroshi Miyanaga, Yousuke Yamamoto:
High-Speed Time Division Switch for 32-Mbit/s Bearer Rate Signals. IEEE J. Sel. Areas Commun. 5(8): 1249-1255 (1987)
1986
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Yousuke Yamamoto, Hiroshi Miyanaga, Yoshiji Kobayashi, Yasukazu Terada, Naoaki Yamanaka:
A Novel Concept for High-Speed Time Switch Approaching Memory Read Cycle Limit. IEEE Trans. Commun. 34(9): 953-955 (1986)

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