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ORCIDPranose J. Edavoor
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2020 – today
- 2024
[j11]Aswini K. Samantaray
, Pranose J. Edavoor, Amol D. Rahulkar:
A Novel Design Approach and VLSI Architecture of Rationalized Bi-Orthogonal Wavelet Filter Banks. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 619-632 (2024)- [c10]Gopal Raut, Pranose J. Edavoor, David Selvakumar, Ritambhara Thakur:
A SIMD Dynamic Fixed Point Processing Engine for DNN Accelerators. ISQED 2024: 1-8 - 2023
- [j10]Aswini K. Samantaray, Pranose J. Edavoor, Amol D. Rahulkar:
Power-Efficient VLSI Architecture of a New Class of Dyadic Gabor Wavelets for Medical Image Retrieval. IEEE Trans. Very Large Scale Integr. Syst. 31(1): 104-113 (2023) - [c9]Pranose J. Edavoor, Aneesh Raveendran, David Selvakumar, Vivian Desalphine, Shankar G. Dharani, Gopal Raut:
Design and Analysis of Posit Quire Processing Engine for Neural Network Applications. VLSID 2023: 252-257 - 2022
- [j9]Aswini K. Samantaray, Pranose J. Edavoor, Amol D. Rahulkar:
A Novel Design of Symmetric Daub-4 Wavelet Filter Bank for Image Analysis. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3949-3953 (2022) - [j8]Aswini K. Samantaray, Pranose J. Edavoor, Amol D. Rahulkar:
A New Approach to the Design and Implementation of a Family of Multiplier Free Orthogonal Wavelet Filter Banks. IEEE Trans. Circuits Syst. Video Technol. 32(4): 1942-1954 (2022) - [c8]Sithara Raveendran, Pranose J. Edavoor, Y. B. Nithin Kumar, M. H. Vasantha:
On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic. ISCAS 2022: 3428-3432 - 2021
- [j7]Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, M. H. Vasantha:
Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic. IEEE Access 9: 108119-108130 (2021) - [j6]Aswini K. Samantaray, Amol D. Rahulkar, Pranose J. Edavoor:
A Novel Design of Dyadic db3 Orthogonal Wavelet Filter Bank for Feature Extraction. Circuits Syst. Signal Process. 40(11): 5401-5420 (2021) - [j5]Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar:
Novel 4: 2 Approximate Compressor Designs for Multimedia and Neural Network Applications. J. Circuits Syst. Comput. 30(8): 2150138:1-2150138:27 (2021) - 2020
- [j4]Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar:
Approximate Multiplier Design Using Novel Dual-Stage 4: 2 Compressors. IEEE Access 8: 48337-48351 (2020) - [j3]Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha:
An Approximate Low-Power Lifting Scheme Using Reversible Logic. IEEE Access 8: 183367-183377 (2020) - [j2]Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra:
Design and implementation of image kernels using reversible logic gates. IET Image Process. 14(16): 4110-4121 (2020) - [c7]Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Y. B., M. H. Vasantha:
Reversible Logic Implementation of Image Denoising for Grayscale Images. MWSCAS 2020: 138-141
2010 – 2019
- 2019
- [j1]Pranose J. Edavoor, Amol D. Rahulkar:
Design and implementation of a novel low complexity symmetric orthogonal wavelet filter-bank. IET Image Process. 13(5): 785-793 (2019) - 2018
- [c6]Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha:
Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter. TENCON 2018: 1813-1817 - 2017
- [c5]Priyanandini Das, Pranose J. Edavoor, Sithara Raveendran, Sunil Rathore, Amol D. Rahulkar:
Design and implementation of PID controller based on orthogonal wavelet filter-banks in FPGA. ISED 2017: 1-6 - [c4]Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar:
Implementation of adaptive image compression algorithm using varying bit-length daubechies wavelet coefficient with three-level encryption on Zynq 7000. ISED 2017: 1-6 - 2016
- [c3]Pranose J. Edavoor, Sithara Raveendran, Arjun T. V., Sumesh K. P., Kumar Y. B. Nithin, M. H. Vasantha:
FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images. ICCCNT 2016: 35:1-35:6 - 2015
- [c2]B. Naresh Kumar Reddy, N. Suresh, Janjhyam Venkata Naga Ramesh, T. Pavithra, Y. Krupa Bahulya, Pranose J. Edavoor, S. Janaki Ram:
An efficient approach for design and testing of FPGA programming using Lab VIEW. ICACCI 2015: 543-548 - [c1]K. Jayasree, B. Naresh Kumar Reddy, B. Srinuvasu Kumar, Janjhyam Venkata Naga Ramesh, Pranose J. Edavoor, Mohd Kashif Zia Ansari:
Poster: An Efficient Low Power & High Performance in MPSOC. WCI 2015: 708-711
Coauthor Index
aka: Nithin Y. B. Kumar
aka: Nithin Kumar Y. B.
aka: Kumar Y. B. Nithin
aka: Y. B. Nithin Kumar
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