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2020 – today
- 2020
[c12]Huidong Tang, Yuichiro Mori, Masahiko Toyonga:
A Tiny Neural Network Model for Estimating Next 24 Hour Temperature Transition. ICSSE 2020: 1-6
2010 – 2019
- 2018
- [c11]Kenya Murata, Masataka Mito, Daisuke Eguchi, Yuichiro Mori, Masahiko Toyonaga:
A Single Filter CNN Performance for Basic Shape Classification. iCAST 2018: 139-143 - [c10]Masataka Mito, Kenya Murata, Daisuke Eguchi, Yuichiro Mori, Masahiko Toyonaga:
A Data Reconstruction Method for The Big-Data Analysis. iCAST 2018: 319-323 - [c9]Keisuke Yabunaka, Yuichiro Mori, Masahiko Toyonaga:
Facial Expression Sequence Recognition for a Japanese Sign Language Training System. SCIS&ISIS 2018: 1348-1353 - [c8]Yuichiro Mori, Masahiko Toyonaga:
Data-Glove for Japanese Sign Language Training System with Gyro-Sensor. SCIS&ISIS 2018: 1354-1357 - 2014
- [c7]Yusuke Morimoto, Mitsuru Matsushita, Michiaki Muraoka, Masahiko Toyonaga:
A critical net reshape-router for high-performance VLSI layout design. APCCAS 2014: 587-590 - 2013
- [c6]Tingyuan Nie, Yansheng Li, Lijian Zhou, Masahiko Toyonaga:
A multilevel fingerprinting method for FPGA IP protection. ISCAS 2013: 1789-1792 - [c5]Yoshiya Fujii, Michiaki Muraoka, Masahiko Toyonaga:
A multilayer crosstalk avoidance router using restricted maze grids. MWSCAS 2013: 641-644
2000 – 2009
- 2007
- [j2]Tingyuan Nie, Masahiko Toyonaga:
An Efficient and Reliable Watermarking System for IP Protection. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(9): 1932-1939 (2007) - 2005
- [c4]Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga:
A watermarking system for IP protection by a post layout incremental router. DAC 2005: 218-221 - [c3]Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga:
A post layout watermarking method for IP protection. ISCAS (6) 2005: 6206-6209 - 2002
- [j1]Keiichi Kurokawa, Takuya Yasui, Yoichi Matsumura, Masahiko Toyonaga, Atsushi Takahashi:
A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2746-2755 (2002) - 2000
- [c2]Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi
:
A practical clock tree synthesis for semi-synchronous circuits. ISPD 2000: 159-164
1990 – 1999
- 1994
- [c1]Masahiko Toyonaga, Shih-Tsung Yang, Toshiro Akino, Isao Shirakawa:
A New Approach of Fractional-Dimension Based Module Clustering for VLSI Layout. ISCAS 1994: 185-188
Coauthor Index
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