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Geum-Young Tak

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Journal Articles

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2018
[j3]
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Geum-Young Tak, Kwyro Lee:
A Low-Reference Spur MDLL-Based Clock Multiplier and Derivation of Discrete-Time Noise Transfer Function for Phase Noise Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(2): 485-497 (2018)
2016
[j2]
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Heein Yoon, Yongsun Lee, Younghyun Lim, Geum-Young Tak, Hong-Teuk Kim, Yo-Chuol Ho, Jaehyouk Choi:
A 0.56-2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G-4G Multistandard Cellular Transceivers. IEEE J. Solid State Circuits 51(3): 614-625 (2016)
2005
[j1]
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Geum-Young Tak, Seok-Bong Hyun, Tae Young Kang, Byoung Gun Choi, Seong Su Park:
A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications. IEEE J. Solid State Circuits 40(8): 1671-1679 (2005)

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