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2020 – today
- 2025
[j16]Qiqiao Wu
, Honghu Yang, Yixuan Liu, Yue Cao, Yongkang Han, Haijun Jiang, Keji Zhou, Hailan Yi, Jianguo Yang, Qi Liu:
A Novel Neuromorphic Hardware Using Area-Efficient Chain RRAM-Based Synapses and Compact Neurons With (Anti-) Integration Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 72(3): 1383-1396 (2025)- [j15]Yixuan Liu, Qiqiao Wu, Honghu Yang, Chengshuo Yu, Keji Zhou, Yu Jiang, Haijun Jiang, Hailan Yi, Xiaoyong Xue, Jianguo Yang, Xiaoyang Zeng:
Enhancing All-to-All RRAM Ising Machines With Randomized Granular Update Strategies for Solving Combinatorial Optimization Problems. IEEE Trans. Circuits Syst. I Regul. Pap. 72(9): 4877-4890 (2025) - [c7]Tianci Cai, Qiqiao Wu, Yixuan Liu, Yue Cao, Yu Jiang, Keji Zhou, Jianguo Yang:
SRIF: Energy- and Area-Efficient Soft Reset Integrate-and-Fire Neuron for High-Accuracy Spiking Neural Network. ISCAS 2025: 1-5 - [c6]Yue Cao, Yuanyuan Han, Keji Zhou, Chengshuo Yu, Tianci Cai, Jianguo Yang:
A Refresh-Reduction Digital eDRAM CIM Macro using Asymmetric Error Tolerance Scheme. ISCAS 2025: 1-5 - [c5]Jingxin Deng, Keji Zhou, Honghu Yang, Chengshuo Yu, Jianguo Yang:
A High-Density RRAM-Based Ising Machine with Analog In-Memory Operation for Solving Combinatorial Optimization Problems. ISCAS 2025: 1-5 - [c4]Honghu Yang, Yongkang Han, Tianci Cai, Chengshuo Yu, Keji Zhou, Jianguo Yang:
A High Performance Dual-Wordline RRAM Macro with Replica Bitline Delay Control Circuit. ISCAS 2025: 1-5 - 2024
- [j14]Siyuan Ouyang, Keji Zhou, Hao Jiang, Chenyang Li, Jinhao Liang, Fangduo Zhu, Xumeng Zhang, Qi Liu:
A Scalable Area-Efficient Low-Delay Asynchronous AER Circuits Design for Neuromorphic Chips. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2804-2808 (2024) - [j13]Shiwei Liu, Chen Mu, Hao Jiang, Yunzhengmao Wang, Jinshan Zhang, Feng Lin, Keji Zhou, Qi Liu, Chixiao Chen:
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 269-282 (2024) - 2023
- [j12]Hao Jiang, Jikai Lu, Chenggao Zhang, Shuangzhu Tang, Junjie An, Lingli Cheng, Jian Lu, Jinsong Wei, Keji Zhou, Xumeng Zhang, Tuo Shi, Qi Liu:
Multicore Spiking Neuromorphic Chip in 180-nm With ReRAM Synapses and Digital Neurons. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(4): 975-985 (2023) - [j11]Jingwen Jiang, Keji Zhou, Jinhao Liang, Fengshi Tian, Chenyang Zhao, Jianguo Yang, Xiaoyong Xue, Xiaoyang Zeng:
Tempo-CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator With Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(4): 986-999 (2023) - [j10]Deyang Chen, Zhiwang Guo, Jinbei Fang, Chenyang Zhao, Jingwen Jiang, Keji Zhou, Haidong Tian, Xiankui Xiong, Xiaoyong Xue, Xiaoyang Zeng:
A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications. IEEE Trans. Circuits Syst. II Express Briefs 70(1): 276-280 (2023) - [j9]Zhiwang Guo, Deyang Chen, Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Yixuan Liu, Haidong Tian, Xiankui Xiong, Keji Zhou, Xiaoyong Xue, Qi Liu, Xiaoyang Zeng:
An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices. IEEE Trans. Circuits Syst. II Express Briefs 70(7): 2645-2649 (2023) - 2022
- [j8]Faming Li, Sheng Cui, Yanan Chen, Chenjie Rao, Yicong Tu, Keji Zhou, Deming Liu:
Toward Practical Temporal Diversity Coherent Combining Based Variable Data-Rate Free Space Optical Communication Systems. IEEE Access 10: 79480-79490 (2022) - [j7]Keji Zhou, Xinru Jia, Chenyang Zhao, Xumeng Zhang, Guangjian Wu, Chen Mu, Haozhe Zhu, Yanting Ding, Chixiao Chen, Xiaoyong Xue, Xiaoyang Zeng, Qi Liu:
A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(4): 846-857 (2022) - [j6]Keji Zhou, Ruijun Lin, Zhiwang Guo, Yixuan Liu, Jingwen Jiang, Chenyang Zhao, Jinbei Fang, Xiaoxin Xu, Xiaoyong Xue, Xiaoyang Zeng:
A 2D2R ReRAM CIM accelerator for multilayer perceptron in visual classification applications. Microelectron. J. 125: 105478 (2022) - [j5]Jianguo Yang, Ruijun Lin, Keji Zhou, Yuejun Zhang, Xiaoyong Xue, Hangbing Lv:
A 28 nm 512 Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for high density and low BER cryptographic key in IoT devices. Microelectron. J. 128: 105550 (2022) - [c3]Chen Mu, Yunzhengmao Wang, Jiapei Zheng, Shiwei Liu, Keji Zhou, Shan Tang, Chixiao Chen, Qi Liu:
A 200M-Query-Vector/s Computing-in-RRAM ADC-less k-Nearest-Neighbor Accelerator with Time-Domain Winner-Takes-All Circuits. AICAS 2022: 222-225 - 2021
- [j4]Keji Zhou, Xiaoyong Xue, Jianguo Yang, Xiaoxin Xu, Hangbing Lv, Ming-e Jing, Jing Li, Xiaoyang Zeng, Ming Liu:
High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications. IEEE J. Solid State Circuits 56(3): 988-1000 (2021) - [j3]Keji Zhou, Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Deyang Chen, Yujie Huang, Ming-e Jing, Jun Han, Haidong Tian, Xiankui Xiong, Qi Liu, Xiaoyong Xue, Xiaoyang Zeng:
An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(8): 2932-2936 (2021) - 2020
- [j2]Chenjie Rao, Sheng Cui, Yicong Tu, Keji Zhou, Deming Liu:
Toward Practical Digital Phase Alignment for Coherent Beam Combining in Multi-Aperture Free Space Coherent Optical Receivers. IEEE Access 8: 202585-202595 (2020)
2010 – 2019
- 2019
- [c2]Yujie Cai, Keji Zhou, Xiaoyong Xue, Mingyu Wang, Xiaoyang Zeng:
Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications. ASICON 2019: 1-4 - 2018
- [c1]Keji Zhou, Xiaoyong Xue, Jianguo Yang, Xiaoxin Xu, Hangbing Lv, Mingyu Wang, Ming-e Jing, Wenjun Liu, Xiaoyang Zeng, Steve S. Chung, Jing Li, Ming Liu:
Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F2 and K-means Clustering for Power Reduction. A-SSCC 2018: 135-138 - 2016
- [j1]Liang Wen, Xu Cheng, Keji Zhou, Shudong Tian, Xiaoyang Zeng:
Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 63-II(7): 643-647 (2016)
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