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Giulio Stramondo
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2020 – today
- 2020
- [j1]Giulio Stramondo
, Catalin Bogdan Ciobanu
, Cees de Laat, Ana Lucia Varbanescu:
Designing and building application-centric parallel memories. Concurr. Comput. Pract. Exp. 32(15) (2020) - [c8]Giulio Stramondo, Manil Dev Gomony
, Bartek Kozicki, Cees de Laat, Ana Lucia Varbanescu:
μ-Genie: A Framework for Memory-Aware Spatial Processor Architecture Co-Design Exploration. DSD 2020: 180-184
2010 – 2019
- 2018
- [c7]Giulio Stramondo, Catalin Bogdan Ciobanu
, Ana Lucia Varbanescu, Cees de Laat:
Towards Application-Centric Parallel Memories. Euro-Par Workshops 2018: 481-493 - [c6]Catalin Bogdan Ciobanu
, Giulio Stramondo, Cees de Laat, Ana Lucia Varbanescu:
MAX-PolyMem: High-Bandwidth Polymorphic Parallel Memories for DFEs. IPDPS Workshops 2018: 107-114 - [c5]Catalin Bogdan Ciobanu
, Giulio Stramondo, Ana Lucia Varbanescu, Andreas Brokalakis, Antonis Nikitakis, Lorenzo Di Tucci, Marco Rabozzi, Luca Stornaiuolo, Marco D. Santambrogio, Grigorios Chrysos, Charalampos Vatsolakis, Georgios Charitopoulos, Dionisios N. Pnevmatikatos
:
EXTRA: an open platform for reconfigurable architectures. SAMOS 2018: 220-229 - [c4]Luca Stornaiuolo, Marco Rabozzi, Marco D. Santambrogio, Donatella Sciuto, Catalin Bogdan Ciobanu
, Giulio Stramondo, Ana Lucia Varbanescu:
Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS. VLSI-SoC (Selected Papers) 2018: 53-78 - [c3]Luca Stornaiuolo, Marco Rabozzi, Donatella Sciuto, Marco D. Santambrogio, Giulio Stramondo, Catalin Bogdan Ciobanu
, Ana Lucia Varbanescu:
HLS Support for Polymorphic Parallel Memories. VLSI-SoC 2018: 143-148 - 2017
- [c2]Amit Kulkarni, Poona Bahrebar, Dirk Stroobandt, Giulio Stramondo, Catalin Bogdan Ciobanu
, Ana Lucia Varbanescu:
A NoC-based custom FPGA configuration memory architecture for ultra-fast micro-reconfiguration. FPT 2017: 203-206 - 2016
- [c1]Giuseppe Natale, Giulio Stramondo, Pietro Bressana, Riccardo Cattaneo, Donatella Sciuto, Marco D. Santambrogio:
A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops. ICCAD 2016: 77
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