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ORCIDEdwin Thaller
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2020 – today
- 2021
[c4]Edwin Thaller, Run Levinger, Evgeny Shumaker, Aryeh Farber, Sergey Bershansky, Nir Geron, Ashoke Ravi, Rotem Banin, Jasmin Kadry, Gil Horovitz, Christian Krassnitzer, Christoph Duller, Patrick Torta, Mark Elzinga, Kamran Azadet:
A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS. ISSCC 2021: 451-453
2010 – 2019
- 2017
- [c3]Antonio Passamani, Davide Ponton, Edwin Thaller, Gerhard Knoblinger, Andrea Neviani
, Andrea Bevilacqua:
13.9 A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE. ISSCC 2017: 232-233 - 2016
- [c2]Stefan Trampitsch, Daniel Gruber, Michael Lunglmayr, Edwin Thaller, Mario Huemer:
Digital compensation of DC-DC converter voltage ripple for Switched-Capacitor Power Amplifiers. NEWCAS 2016: 1-4
2000 – 2009
- 2005
- [j1]Nicola Da Dalt, Edwin Thaller, Peter Gregorius, Lajos Gazsi:
A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS. IEEE J. Solid State Circuits 40(7): 1482-1490 (2005) - 2004
- [c1]Nicola Da Dalt, Edwin Thaller, Peter Gregorius, Lajos Gazsi:
A low jitter triple-band digital LC PLL in 130nm CMOS. ESSCIRC 2004: 371-374
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