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Joo-Hyung Chae
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2020 – today
- 2024
- [c13]Ho-Sung Lee, Joo-Hyung Chae:
A 1-Kb 6T 1C XNOR-DRAM Compute-In-Memory Macro With Signed Bit Adder Block for CNN Operations. ICEIC 2024: 1-4 - [c12]Chanheum Han, Ki-Soo Lee, Joo-Hyung Chae:
13.9 A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency. ISSCC 2024: 248-250 - 2023
- [j20]Jaewook Kim, Jaekwang Yun, Joo-Hyung Chae
, Suhwan Kim
:
A 50-1600 MHz Wide-Range Digital Duty-Cycle Corrector With Counter-Based Half-Cycle Delay Line. IEEE Access 11: 30555-30561 (2023) - [j19]Yong-Un Jeong
, Joo-Hyung Chae
, Suhwan Kim
:
A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces. IEEE J. Solid State Circuits 58(9): 2659-2667 (2023) - [j18]Yong-Un Jeong
, Sungphil Choi
, Suhwan Kim
, Joo-Hyung Chae
:
Single-Ended Receiver-Side Crosstalk Cancellation With Independent Gain and Timing Control for Minimum Residual FEXT. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4793-4803 (2023) - [j17]Joo-Hyung Chae
:
Design of Clocked Comparator Preventing Bit Errors to Improve Reliability of Low-Speed DRAM Measurement. IEEE Trans. Instrum. Meas. 72: 1-10 (2023) - [c11]Jun-Cheol Lee, Tae-Oh Kim, Joo-Hyung Chae:
Module Implementation and Simulation of Timing Constraint Check Function of I2C Protocol Using Verilog. ICEIC 2023: 1-4 - 2022
- [j16]Joo-Hyung Chae
, Yong-Un Jeong
, Byung-Du Choi
:
Design and Comparative Study of Voltage Regulation-Based 2-Tap Flexible Feed-Forward Equalizer for Voltage-Mode Transmitters. IEEE Access 10: 37446-37456 (2022) - [j15]Jihyo Kang
, Jaehyeok Yang
, Kyunghoon Kim, Joo-Hyung Chae
, Gang-Sik Lee, Sang-Yeon Byeon, Boram Kim, Dong-Hyun Kim, Youngtaek Kim
, Yeongmuk Cho, Junghwan Ji, Sera Jeong, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Sunho Kim, Hae-Kang Jung, Jieun Jang
, Sangkwon Lee
, Hyungsoo Kim, Joo-Hwan Cho, Junhyun Chun, Seon-Yong Cha:
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation. IEEE J. Solid State Circuits 57(1): 212-223 (2022) - [j14]Yong-Un Jeong
, Sungphil Choi
, Joo-Hyung Chae
, Jaekwang Yun, Shin-Hyun Jeong
, Suhwan Kim
:
A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1125-1134 (2022) - [j13]Sangyoon Lee
, Yong-Un Jeong
, Jaekwang Yun, Joo-Hyung Chae
, Suhwan Kim
:
A Low-Power DRAM Transmitter With Phase and Current-Mode Amplitude Equalization to Improve Impedance Matching. IEEE Trans. Circuits Syst. II Express Briefs 69(11): 4208-4212 (2022) - 2021
- [j12]Sungphil Choi
, Yong-Un Jeong
, Joo-Hyung Chae
, Shin-Hyun Jeong
, Suhwan Kim
:
A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface. IEEE Access 9: 120285-120296 (2021) - [j11]Yong-Un Jeong
, Hyunkyu Park
, Changho Hyun, Joo-Hyung Chae
, Shin-Hyun Jeong
, Suhwan Kim
:
A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface. IEEE J. Solid State Circuits 56(4): 1278-1287 (2021) - [j10]Hyeongjun Ko
, Mino Kim, Hyunkyu Park
, Sangyoon Lee
, Jaewook Kim, Suhwan Kim
, Joo-Hyung Chae
:
A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer. IEEE J. Solid State Circuits 56(8): 2563-2573 (2021) - [c10]Hyunkyu Park, Jihwan Park, Jae-Whan Lee, Yong-Un Jeong, Shin-Hyun Jeong, Suhwan Kim, Joo-Hyung Chae:
A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces. ISCAS 2021: 1-5 - [c9]Kyunghoon Kim, Joo-Hyung Chae
, Jaehyeok Yang, Jihyo Kang, Gang-Sik Lee, Sang-Yeon Byeon, Youngtaek Kim, Boram Kim, Dong-Hyun Kim, Yeongmuk Cho, Kangmoo Choi, Hyeongyeol Park, Junghwan Ji, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Kyubong Kong, Sunho Kim, Sangkwon Lee, Junhyun Chun, Hyungsoo Kim, Seon-Yong Cha:
A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation. ISSCC 2021: 344-346 - 2020
- [j9]Joo-Hyung Chae
, Minchang Kim, Sungphil Choi
, Suhwan Kim
:
A 10.4-Gb/s 1-Tap Decision Feedback Equalizer With Different Pull-Up and Pull-Down Tap Weights for Asymmetric Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 67-II(2): 220-224 (2020) - [j8]Yong-Un Jeong
, Jihwan Park, Mino Kim, Joo-Hyung Chae
, Jaekwang Yun, Hyunjoong Lee
, Suhwan Kim
:
A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1589-1593 (2020) - [j7]Joo-Hyung Chae
, Yong-Un Jeong
, Suhwan Kim
:
Data-Dependent Selection of Amplitude and Phase Equalization in a Quarter-Rate Transmitter for Memory Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(9): 2972-2983 (2020) - [j6]Sangyoon Lee
, Han-Gon Ko
, Joo-Hyung Chae
, Soyeong Shin
, Jaekwang Yun, Deog-Kyoon Jeong
, Suhwan Kim
:
A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1735-1739 (2020)
2010 – 2019
- 2019
- [j5]Joo-Hyung Chae
, Hyeongjun Ko, Jihwan Park, Suhwan Kim
:
A 12.8-Gb/s Quarter-Rate Transmitter Using a 4: 1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 372-376 (2019) - [j4]Joo-Hyung Chae
, Hyeongjun Ko, Jihwan Park, Suhwan Kim
:
A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 978-982 (2019) - [c8]Changho Hyun, Hyeongjun Ko, Joo-Hyung Chae
, Hyunkyu Park, Suhwan Kim:
A 20Gb/s Dual-Mode PAM4/NRZ Single-Ended Transmitter with RLM Compensation. ISCAS 2019: 1-4 - [c7]Yong-Un Jeong, Joo-Hyung Chae
, Sungphil Choi, Jaekwang Yun, Shin-Hyun Jeong, Suhwan Kim:
A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS. ISLPED 2019: 1-6 - 2018
- [j3]Joo-Hyung Chae
, Mino Kim, Gi-Moon Hong, Jihwan Park, Suhwan Kim
:
A 3.2 Gb/s 16-Channel Transmitter for Intra-Panel Interfaces, With Independently Controllable Output Swing, Common-Mode Voltage, and Equalization. IEEE Access 6: 78055-78064 (2018) - [j2]Jihwan Park, Joo-Hyung Chae
, Yong-Un Jeong, Jae-Whan Lee, Suhwan Kim
:
A 2.1-Gb/s 12-Channel Transmitter With Phase Emphasis Embedded Serializer for 55-in UHD Intra-Panel Interface. IEEE J. Solid State Circuits 53(10): 2878-2888 (2018) - [j1]Mino Kim, Joo-Hyung Chae
, Sungphil Choi
, Gi-Moon Hong, Hyeongjun Ko, Deog-Kyoon Jeong
, Suhwan Kim
:
A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1894-1898 (2018) - [c6]Jae-Whan Lee, Joo-Hyung Chae
, Jihwan Park, Hyunkyu Park, Jaekwang Yun, Suhwan Kim:
Energy-Efficient Dynamic Comparator with Active Inductor for Receiver of Memory Interfaces. ISLPED 2018: 10:1-10:6 - 2017
- [c5]Jihwan Park, Joo-Hyung Chae
, Yong-Un Jeong, Jae-Whan Lee, Suhwan Kim:
A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for UHD intra-panel interface. A-SSCC 2017: 257-260 - [c4]Jihwan Park, Gi-Moon Hong, Mino Kim, Joo-Hyung Chae
, Suhwan Kim:
A 0.13pJ/bit, referenceless transceiver with clock edge modulation for a wired intra-BAN communication. ISLPED 2017: 1-6 - [c3]Minchang Kim, Jihwan Park, Joo-Hyung Chae
, Hyeongjun Ko, Mino Kim, Suhwan Kim:
An 8Gb/s adaptive DFE with level calibration using training data pattern for mobile DRAM interface. ISOCC 2017: 286-287 - 2015
- [c2]Joo-Hyung Chae
, Gi-Moon Hong, Jihwan Park, Mino Kim, Hyeongjun Ko, Woo-Yeol Shin, Hankyu Chi, Deog-Kyoon Jeong, Suhwan Kim:
A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers. A-SSCC 2015: 1-4 - 2013
- [c1]Mino Kim, Woo-Yeol Shin, Gi-Moon Hong, Jihwan Park, Joo-Hyung Chae
, Nan Xing, Jong-Kwan Woo, Suhwan Kim:
High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line. ESSCIRC 2013: 311-314
Coauthor Index
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last updated on 2024-04-25 05:45 CEST by the dblp team
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