
BibTeX records: Gururaj Saileshwar
@article{DBLP:journals/corr/abs-2009-09090, author = {Gururaj Saileshwar and Moinuddin K. Qureshi}, title = {{MIRAGE:} Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative Design}, journal = {CoRR}, volume = {abs/2009.09090}, year = {2020}, url = {https://arxiv.org/abs/2009.09090}, archivePrefix = {arXiv}, eprint = {2009.09090}, timestamp = {Wed, 23 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/abs-2009-09090.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/SaileshwarQ19, author = {Gururaj Saileshwar and Moinuddin K. Qureshi}, title = {CleanupSpec: An "Undo" Approach to Safe Speculation}, booktitle = {Proceedings of the 52nd Annual {IEEE/ACM} International Symposium on Microarchitecture, {MICRO} 2019, Columbus, OH, USA, October 12-16, 2019}, pages = {73--86}, publisher = {{ACM}}, year = {2019}, url = {https://doi.org/10.1145/3352460.3358314}, doi = {10.1145/3352460.3358314}, timestamp = {Wed, 16 Oct 2019 09:55:30 +0200}, biburl = {https://dblp.org/rec/conf/micro/SaileshwarQ19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/abs-1906-02362, author = {Gururaj Saileshwar and Moinuddin K. Qureshi}, title = {Lookout for Zombies: Mitigating Flush+Reload Attack on Shared Caches by Monitoring Invalidated Lines}, journal = {CoRR}, volume = {abs/1906.02362}, year = {2019}, url = {http://arxiv.org/abs/1906.02362}, archivePrefix = {arXiv}, eprint = {1906.02362}, timestamp = {Thu, 13 Jun 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/abs-1906-02362.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hpca/SaileshwarNREQ18, author = {Gururaj Saileshwar and Prashant J. Nair and Prakash Ramrakhyani and Wendy Elsasser and Moinuddin K. Qureshi}, title = {{SYNERGY:} Rethinking Secure-Memory Design for Error-Correcting Memories}, booktitle = {{IEEE} International Symposium on High Performance Computer Architecture, {HPCA} 2018, Vienna, Austria, February 24-28, 2018}, pages = {454--465}, publisher = {{IEEE} Computer Society}, year = {2018}, url = {https://doi.org/10.1109/HPCA.2018.00046}, doi = {10.1109/HPCA.2018.00046}, timestamp = {Wed, 16 Oct 2019 14:14:50 +0200}, biburl = {https://dblp.org/rec/conf/hpca/SaileshwarNREQ18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/SaileshwarNREJQ18, author = {Gururaj Saileshwar and Prashant J. Nair and Prakash Ramrakhyani and Wendy Elsasser and Jos{\'{e}} A. Joao and Moinuddin K. Qureshi}, title = {Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories}, booktitle = {51st Annual {IEEE/ACM} International Symposium on Microarchitecture, {MICRO} 2018, Fukuoka, Japan, October 20-24, 2018}, pages = {416--427}, publisher = {{IEEE} Computer Society}, year = {2018}, url = {https://doi.org/10.1109/MICRO.2018.00041}, doi = {10.1109/MICRO.2018.00041}, timestamp = {Fri, 24 Jan 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/micro/SaileshwarNREJQ18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isocc/KabaraTSBS11, author = {Priyanka Kabara and Sanket Thakur and Gururaj Saileshwar and Maryam Shojaei Baghini and Dinesh Kumar Sharma}, title = {{CMOS} low-noise signal conditioning with a novel differential "resistance to frequency" converter for resistive sensor applications}, booktitle = {International SoC Design Conference, {ISOCC} 2011, Jeju, South Korea, November 17-18, 2011}, pages = {298--301}, publisher = {{IEEE}}, year = {2011}, url = {https://doi.org/10.1109/ISOCC.2011.6138769}, doi = {10.1109/ISOCC.2011.6138769}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/isocc/KabaraTSBS11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }

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