Yixiong Yang

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Zhibo Wang 0004

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Publications

2019
[j2]
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Yongpan Liu, Fang Su, Yixiong Yang, Zhibo Wang, Yiqun Wang, Zewei Li, Xueqing Li, Ryuji Yoshimura, Takashi Naiki, Takashi Tsuwa, Takahiko Saito, Zhongjun Wang, Koji Taniuchi, Huazhong Yang:
A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System. IEEE J. Solid State Circuits 54(3): 885-895 (2019)
[j1]
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Yixiong Yang, Xin Shi, Fang Su, Zhibo Wang, Pei Yang, Huazhong Yang, Yongpan Liu:
A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(5): 1970-1980 (2019)
[c6]
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Zhe Yuan, Jingyu Wang, Yixiong Yang, Jinshan Yue, Zhibo Wang, Xiaoyu Feng, Yanzhi Wang, Xueqing Li, Huazhong Yang, Yongpan Liu:
A Sparse-Adaptive CNN Processor with Area/Performance balanced N-Way Set-Associate PE Arrays Assisted by a Collision-Aware Scheduler. A-SSCC 2019: 61-64
2018
[c3]
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Yixiong Yang, Zhibo Wang, Pei Yang, Meng-Fan Chang, Mon-Shu Ho, Huazhong Yang, Yongpan Liu:
A 2-GHz Direct Digital Frequency Synthesizer Based on LUT and Rotation. ISCAS 2018: 1-5
[c2]
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Zhe Yuan, Jinshan Yue, Huanrui Yang, Zhibo Wang, Jinyang Li, Yixiong Yang, Qingwei Guo, Xueqing Li, Meng-Fan Chang, Huazhong Yang, Yongpan Liu:
Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers. VLSI Circuits 2018: 33-34

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