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Gioele Mirabelli
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2020 – today
- 2023
- [c6]Devin Verreck, Piet Wambacq, Maarten Van De Put, Zubair Ahmed, Quentin Smets, Aryan Afzalian, Rutger Duflou, Xiangyu Wu, Gioele Mirabelli, Rongmei Chen, Inge Asselberghs, Gouri Sankar Kar:
The Promise of 2-D Materials for Scaled Digital and Analog Applications. ISSCC 2023: 394-395 - [c5]Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Yun Zhou
, Ivan Ciofi, Anne Jourdain, A. Veloso, Michele Stucchi, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert:
Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. VLSI Technology and Circuits 2023: 1-2 - [c4]S. Yang, Pieter Schuddinck, Marie Garcia Bardon, Yang Xiang, Anabela Veloso, B. T. Chan, Gioele Mirabelli, Gaspard Hiblot, Geert Hellings, Julien Ryckaert:
PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c3]Odysseas Zografos, Bilal Chehab, Pieter Schuddinck, Gioele Mirabelli, Naveen Kakarla, Yang Xiang, Pieter Weckx, Julien Ryckaert:
Design enablement of CFET devices for sub-2nm CMOS nodes. DATE 2022: 29-33 - [c2]Pieter Schuddinck, Fabian M. Bufler, Yang Xiang, Anita Farokhnejad, Gioele Mirabelli, Anne Vandooren, Bilal Chehab, A. Gupta, César Roda Neve, Geert Hellings, Julien Ryckaert:
PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch. VLSI Technology and Circuits 2022: 365-366
2010 – 2019
- 2017
- [c1]Gioele Mirabelli
, Farzan Gity
, Scott Monaghan, Paul K. Hurley, Ray Duffy
:
Impact of impurities, interface traps and contacts on MoS2 MOSFETs: Modelling and experiments. ESSDERC 2017: 288-291
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