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ORCIDMauricio Vanegas
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2010 – 2019
- 2017
[j11]Agostino Gibaldi
, Mauricio Vanegas, Andrea Canessa, Silvio P. Sabatini:
A Portable Bio-Inspired Architecture for Efficient Robotic Vergence Control. Int. J. Comput. Vis. 121(2): 281-302 (2017)- 2015
- [j10]Francisco Barranco, Matteo Tomasi, Mauricio Vanegas, Javier Díaz, Sara Granados, Eduardo Ros Vidal:
Hierarchical architecture for motion and depth estimations based on color cues. J. Real Time Image Process. 10(2): 435-452 (2015) - 2013
- [j9]Francisco Barranco, Matteo Tomasi, Javier Díaz, Mauricio Vanegas, Eduardo Ros:
Pipelined architecture for real-time cost-optimized extraction of visual primitives based on FPGAs. Digit. Signal Process. 23(2): 675-688 (2013) - [j8]Silvia Tolu, Mauricio Vanegas, Jesús Alberto Garrido, Niceto R. Luque, Eduardo Ros:
Adaptive and Predictive Control of a Simulated Robot arm. Int. J. Neural Syst. 23(3) (2013) - 2012
- [j7]Silvia Tolu, Mauricio Vanegas, Niceto R. Luque, Jesús Alberto Garrido, Eduardo Ros:
Bio-inspired adaptive feedback error learning architecture for motor control. Biol. Cybern. 106(8-9): 507-522 (2012) - [j6]Matteo Tomasi, Mauricio Vanegas, Francisco Barranco, Javier Díaz, Eduardo Ros:
Massive Parallel-Hardware Architecture for Multiscale Stereo, Optical Flow and Image-Structure Computation. IEEE Trans. Circuits Syst. Video Technol. 22(2): 282-294 (2012) - [j5]Francisco Barranco, Matteo Tomasi, Javier Díaz, Mauricio Vanegas, Eduardo Ros:
Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 20(6): 1058-1067 (2012) - [j4]Matteo Tomasi, Mauricio Vanegas, Francisco Barranco, Javier Díaz, Eduardo Ros:
Real-Time Architecture for a Robust Multi-Scale Stereo Engine on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 20(12): 2208-2219 (2012) - 2011
- [c4]Mauricio Vanegas, Leonardo Rubio, Matteo Tomasi, Javier Díaz, Eduardo Ros:
On-Chip Ego-Motion Estimation Based on Optical Flow. ARC 2011: 206-217 - 2010
- [j3]Mauricio Vanegas, Matteo Tomasi, Javier Díaz, Eduardo Ros Vidal:
Multi-port abstraction layer for FPGA intensive memory exploitation applications. J. Syst. Archit. 56(9): 442-451 (2010) - [j2]Matteo Tomasi, Francisco Barranco, Mauricio Vanegas, Javier Díaz, Eduardo Ros Vidal:
Fine grain pipeline architecture for high performance phase-based optical flow computation. J. Syst. Archit. 56(11): 577-587 (2010) - [j1]Matteo Tomasi, Mauricio Vanegas, Francisco Barranco, Javier Díaz, Eduardo Ros:
High-Performance Optical-Flow Architecture Based on a Multi-Scale, Multi-Orientation Phase-Based Model. IEEE Trans. Circuits Syst. Video Technol. 20(12): 1797-1807 (2010)
2000 – 2009
- 2006
- [c3]Jorge Peña, Mauricio Vanegas, Andrés Valencia:
Digital Hardware Architectures of Kohonen's Self Organizing Feature Maps with Exponential Neighboring Function. ReConFig 2006: 114-121 - 2005
- [c2]Jair Montoya, Juan Osorio, Mauricio Vanegas:
Desarrollo de un Control Difuso de Temperatura para una Lámpara de Calor Radiante para Neonatos. CIIC 2005: 74-82 - [c1]Jorge A. Peña, Andrés Valencia, Mauricio Vanegas:
Digital Hardware Design of a One-Dimensional Kohonen's SOFM with Chessboard Norm and Exponential Neighboring Function. CIIC 2005: 154-161
Coauthor Index
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