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ORCIDKatayoon Basharkhah
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2020 – today
- 2024
[c12]Katayoon Basharkhah, Zainalabedin Navabi:
Event-Based Power Analysis Integrated with Timing Characterization and Logic Simulation. ISVLSI 2024: 684-688- 2023
- [c11]Katayoon Basharkhah, Raheleh Sadat Mirhashemi, Nooshin Nosrati, Mohammad-Javad Zare, Zainalabedin Navabi:
Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction. ETS 2023: 1-6 - 2021
- [c10]Nooshin Nosrati, Katayoon Basharkhah, Hanieh Totonchi Asl, Zahra Mahdavi, Zainalabedin Navabi:
Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester. DTIS 2021: 1-6 - [c9]Mohammad Rasoul Roshanshah
, Katayoon Basharkhah, Zainalabedin Navabi:
Online Testing of a Row-Stationary Convolution Accelerator. ETS 2021: 1-2 - 2020
- [c8]Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Zainalabedin Navabi:
Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations. DDECS 2020: 1-4 - [c7]Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Zainalabedin Navabi:
Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator. DFT 2020: 1-4 - [c6]Katayoon Basharkhah, Rezgar Sadeghi, Nooshin Nosrati, Zainalabedin Navabi:
ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links. VTS 2020: 1-6
2010 – 2019
- 2019
- [c5]Rezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah, Zainalabedin Navabi:
Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling. ETS 2019: 1-6 - [c4]Samira Ahmadi Farsani, Katayoon Basharkhah, Amin Mohaghegh, Zainalabedin Navabi:
From Abstract Modeling of ADAS Applications to an Accelerator-based Hardware Realization. EWDTS 2019: 1-6 - [c3]Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Carna Zivkovic, Christoph Grimm, Zainalabedin Navabi:
Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment. EWDTS 2019: 1-5 - [c2]Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi:
An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements. EWDTS 2019: 1-6 - [c1]Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Zainalabedin Navabi:
An ESL Environment for Modeling Electrical Interconnect Faults. ISVLSI 2019: 88-93 - 2018
- [j1]Siavash Amin-Nejad, Tayyebeh Asgari Gashteroodkhani, Katayoon Basharkhah:
A Comparison of MVDR and LCMV Beamformers' Floating Point Implementations on FPGAs. Wirel. Pers. Commun. 98(2): 1913-1929 (2018)
Coauthor Index
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last updated on 2024-10-02 20:41 CEST by the dblp team
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