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Hyun-Ki Han
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2020 – today
- 2024
- [c8]Hyunki Han, Jeong-Hyun Cho, Woojin Jang
, Yousung Park, Jiho Lee, Hyun-Sik Kim:
28.5 A 94.1%-Efficiency Parallel-SC Hybrid Buck Converter Designed Using VCR-Aware Topology Optimizer for a 4.2A/mm² Current-Density FoM. ISSCC 2024: 464-466 - 2023
- [j2]Min-Woo Ko
, Hyunki Han, Hyun-Sik Kim
:
A Bipolar-Output Switched-Capacitor DC-DC Boost Converter With Residual-Energy-Recycling Regulation and Low Dropout Post-Filtering Techniques. IEEE J. Solid State Circuits 58(5): 1400-1413 (2023) - [c7]Heejun Lee, Hyunki Han, Hyun-Sik Kim:
A 4-to-42V Input, 95.5% Efficiency, 3.2μA-IQ, DC-DC Buck Converter Featuring a Leakage-Emulated Bootstrap Re-fresher and Anti-Deadlock Self-Bias Supply for Battery-Powered Automotive Uses. CICC 2023: 1-2 - 2022
- [c6]Hyun-Ki Han, Min-Woo Ko, Jeong-Hyun Cho, Gyeong-Gu Kang, Seok-Tae Koh, Hong-Hyun Bae, Hyun-Sik Kim:
A Monolithic 48V-to-1V 10A Quadruple Step-Down DC-DC Converter with Hysteretic Copied On-Time 4-Phase Control and 2× Slew Rate All-Hysteretic Mode. VLSI Technology and Circuits 2022: 182-183 - 2021
- [j1]Seok-Tae Koh
, Ji-Hun Lee
, Gyeong-Gu Kang, Hyun-Ki Han, Hyun-Sik Kim
:
A 5-V Dynamic Class-C Paralleled Single-Stage Amplifier With Near-Zero Dead-Zone Control and Current-Redistributive Rail-to-Rail Gm-Boosting Technique. IEEE J. Solid State Circuits 56(12): 3593-3607 (2021) - [c5]Seok-Tae Koh, Ji-Hun Lee, Gyeong-Gu Kang, Hyun-Ki Han, Hyun-Sik Kim
:
A 5V Dynamic Class-C Paralleled Single-Stage Amplifier with Near-Zero Dead-Zone Control and Current-Redistributive Rail-to-Rail Gm-Boosting Technique. ISSCC 2021: 86-88 - [c4]Min-Woo Ko, Hyun-Ki Han, Hyun-Sik Kim
:
17.8 A 90.5%-Efficiency 28.7µ VRMS-Noise Bipolar-Output High-Step-Up SC DC-DC Converter with Energy-Recycled Regulation and Post-Filtering for ±15V TFT-Based LAE Sensors. ISSCC 2021: 270-272
2010 – 2019
- 2018
- [c3]Kiduk Kim, Seunghyun Park, Kye-Seok Yoon, Gyeong-Gu Kang, Hyun-Ki Han, Ji-Su Choi, Min-Woo Ko, Jeong-Hyun Cho, Sangjin Lim, Hyung-Min Lee
, Hyunsik Kim, Kwyro Lee, Gyu-Hyeong Cho:
A 100mK-NETD 100ms-startup-time 80×60 micro-bolometer CMOS thermal imager integrated with a 0.234mm2 1.89μVrms noise 12b biasing DAC. ISSCC 2018: 192-194 - [c2]Min-Woo Ko, Kiduk Kim, Young-Jin Woo, Se-Un Shin, Hyun-Ki Han, Yeunhee Huh, Gyeong-Gu Kang, Jeong-Hyun Cho, Sang-Jin Lim, Se-Hong Park
, Hyung-Min Lee
, Gyu-Hyeong Cho:
A 97% high-efficiency 6μs fast-recovery-time buck-based step-up/down converter with embedded 1/2 and 3/2 charge-pumps for li-lon battery management. ISSCC 2018: 428-430 - [c1]Se-Un Shin, Yeunhee Huh, Yong-Min Ju, Sung-Won Choi, Changsik Shin, Young-Jin Woo, Minseong Choi, Se-Hong Park
, Young-Hoon Sohn, Min-Woo Ko, Youngsin Jo, Hyun-Ki Han, Hyung-Min Lee
, Sung-Wan Hong, Wanyuan Qu, Gyu-Hyeong Cho:
A 95.2% efficiency dual-path DC-DC step-up converter with continuous output current delivery and low voltage ripple. ISSCC 2018: 430-432
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