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ORCIDLingxin Meng
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2020 – today
- 2025
[j6]Junqi Liu, Menglian Zhao, Zhaonan Lu, Lingxin Meng, Zhichao Tan:
A 0.7 V 4.2 μW 13 bit self-timed incremental NC-SMASH ADC with SAR-logic-based integrator. IEICE Electron. Express 22(7): 20250005 (2025)- [j5]Lingxin Meng
, Shuang Song, Menglian Zhao, Zhichao Tan:
A 93.6-dB SNDR Fully Dynamic CT-DT Noise-Shaping SAR ADC With Closed-Loop Capacitively Coupled Two-Stage FIA. IEEE J. Solid State Circuits 60(6): 2084-2095 (2025) - [j4]Shan Zhang, Lingxin Meng, Zhaonan Lu, Shuang Song, Wanyuan Qu, Menglian Zhao, Zhichao Tan:
An 871 nW 96.2 dB SNDR Pipelined Second-Order Noise-Shaping SAR ADC Employing Charge-Efficient CLS-Assisted Residue Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 72(4): 1510-1521 (2025) - [c9]Zexin Wang, Lingxin Meng, Menglian Zhao, Mengyu Li, Shuang Song, Zhichao Tan:
A 1V 9-86 fJ/Conv.Step 72.5dB-SNDR Level-Crossing Pipelined ADC with Triggered Sampling and Level Feedback. CICC 2025: 1-3 - [c8]Lingxin Meng, Menglian Zhao, Zhichao Tan:
SQNR Improvement of Incremental Zoom ADCs with Raised-Order CoI Filter and Dither Injection. ISCAS 2025: 1-4 - 2024
- [j3]Lingxin Meng, Junsheng Chen, Menglian Zhao, Zhichao Tan:
A Partially Feedback NSSAR Embedded Third-Order Delta-Sigma Modulator With Gain-Boosted Two-Stage FIAs. IEEE J. Solid State Circuits 59(9): 2735-2746 (2024) - [c7]Lingxin Meng, Menglian Zhao, Zhichao Tan:
A 93.6dB-SNDR 5kHz-BW Fully Dynamic Hybrid CT-DT Noise Shaping SAR ADC. CICC 2024: 1-2 - [c6]Shan Zhang, Lingxin Meng, Zhaonan Lu, Wanyuan Qu, Shuang Song, Menglian Zhao, Zhichao Tan:
An 871nW 96.2dB-SNDR Pipelined NS SAR ADC Achieving 180.8dB-FoMSNDR with a Charge-Efficient CLS-Assisted Two-Stage FIA. CICC 2024: 1-2 - [c5]Weiqiang Chen, Lingxin Meng, Yining Zhao, Menglian Zhao, Zhichao Tan:
A 0.5V 723nW 84.3dB-SNDR Dynamic Zoom ADC with CLS-Assisted Capacitively-Biased FIA. ISCAS 2024: 1-4 - 2023
- [j2]Lingxin Meng, Yaopeng Hu, Yibo Zhao, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan:
A 1.2-V 2.87-μ W 94.0-dB SNDR Discrete-Time 2-0 MASH Delta-Sigma ADC. IEEE J. Solid State Circuits 58(6): 1636-1645 (2023) - [c4]Lingxin Meng, Junsheng Chen, Menglian Zhao, Zhichao Tan:
An 18.2μW 101.1dB DR Fully-Dynamic ΔΣ ADC with Partially-Feedback Noise-Shaping Quantizer and CLS-Embedded Two-Stage FIAs. ESSCIRC 2023: 393-396 - [c3]Bo Peng, Bowen Peng, Jie Zhou, Xichen Huang, Lingxin Meng, Xunzhang Gao:
Low-Frequency Features Optimization for Transferability Enhancement in Radar Target Adversarial Attack. ICANN (5) 2023: 115-129 - [c2]Xirui Hao, Junsheng Chen, Lingxin Meng, Menglian Zhao, Zhichao Tan:
A 94.6dB-SNDR 50kHz-BW 1-1-1 MASH ADC Using OTA-FIA Based Integrators. ISCAS 2023: 1-4 - 2022
- [c1]Junsheng Chen, Lingxin Meng, Menglian Zhao, Zhichao Tan:
An Energy-Efficient Readout Circuit Based on Incremental Delta-Sigma ADC with Decimation Filter for CMOS Image Sensors. APCCAS 2022: 149-152
2010 – 2019
- 2018
- [j1]Xiushan Cai, Lingxin Meng, Wei Zhang, Leipo Liu:
Inverse optimal design of input-to-state stabilisation for affine nonlinear systems with input delays. Int. J. Syst. Sci. 49(4): 833-847 (2018)
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