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ORCIDAbhishek Patyal
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2020 – today
- 2023
[j4]Abhishek Patyal
, Hung-Ming Chen, Mark Po-Hung Lin, Guan-Qi Fang, Simon Yi-Hung Chen:
Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 266-279 (2023)- [j3]A. K. Thasreefa, Abhishek Patyal, Hao-Yu Chi, Mark Po-Hung Lin, Hung-Ming Chen:
On Reducing LDE Variations in Modern Analog Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1268-1279 (2023) - 2021
- [j2]K. A. Asha, Li En Hsu, Abhishek Patyal, Hung-Ming Chen:
Improving the Quality of FPGA RO-PUF by Principal Component Analysis (PCA). ACM J. Emerg. Technol. Comput. Syst. 17(3): 34:1-34:25 (2021) - 2020
- [j1]Abhishek Patyal, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Wei-Zen Chen:
Exploring Multiple Analog Placements With Partial-Monotonic Current Paths and Symmetry Constraints Using PCP-SP. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5056-5068 (2020) - [c5]Abhishek Patyal, Hung-Ming Chen, Mark Po-Hung Lin:
Late Breaking Results: Pole-aware Analog Placement Considering Monotonic Current Flow and Crossing-Wire Minimization. DAC 2020: 1-2 - [c4]Mark Po-Hung Lin, Hao-Yu Chi, Abhishek Patyal, Zheng-Yao Liu, Jun-Jie Zhao, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Achieving Analog Layout Integrity through Learning and Migration Invited Talk. ICCAD 2020: 55:1-55:8
2010 – 2019
- 2018
- [c3]K. A. Asha, Abhishek Patyal, Hung-Ming Chen:
Generation of PUF-Keys on FPGAs by K-means Frequency Clustering. AsianHOST 2018: 44-49 - [c2]Abhishek Patyal, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Hao-Yu Chi, Chien-Nan Liu:
Analog placement with current flow and symmetry constraints using PCP-SP. DAC 2018: 10:1-10:6 - [c1]Po-Cheng Pan, Hung-Wen Huang, Chien-Chia Huang, Abhishek Patyal, Hung-Ming Chen, Tsun-Yu Yang:
On Closing the Gap Between Pre-Simulation and Post-Simulation Results in Nanometer Analog Layouts. SMACD 2018: 181-184
Coauthor Index
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