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Mario Mercandelli
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2020 – today
- 2022
- [j8]Mario Mercandelli
, Alessio Santiccioli
, Angelo Parisi
, Luca Bertulessi
, Dmytro Cherniak, Andrea L. Lacaita
, Carlo Samori
, Salvatore Levantino
:
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter. IEEE J. Solid State Circuits 57(2): 505-517 (2022) - [j7]Simone Mattia Dartizio
, Francesco Tesolin
, Mario Mercandelli
, Alessio Santiccioli
, Abanob Shehata
, Saleh Karman
, Luca Bertulessi
, Francesco Buccoleri
, Luca Avallone
, Angelo Parisi
, Andrea L. Lacaita
, Michael Peter Kennedy
, Carlo Samori
, Salvatore Levantino
:
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping. IEEE J. Solid State Circuits 57(6): 1723-1735 (2022) - [j6]Luca Bertulessi
, Dmytro Cherniak
, Mario Mercandelli
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise. IEEE Trans. Circuits Syst. I Regul. Pap. 69(5): 1858-1870 (2022) - [j5]Gabriele Bè
, Angelo Parisi
, Luca Bertulessi
, Luca Ricci, Lorenzo Scaletti
, Mario Mercandelli
, Andrea L. Lacaita
, Salvatore Levantino
, Carlo Samori
, Andrea Bonfanti
:
A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3645-3649 (2022) - [c8]Lorenzo Scaletti
, Gabriele Bè
, Angelo Parisi, Luca Bertulessi
, Luca Ricci, Mario Mercandelli, Salvatore Levantino, Carlo Samori, Andrea Bonfanti:
A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters. NEWCAS 2022: 20-24 - 2021
- [j4]Luca Avallone
, Mario Mercandelli
, Alessio Santiccioli
, Michael Peter Kennedy
, Salvatore Levantino
, Carlo Samori
:
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2775-2786 (2021) - [c7]Mario Mercandelli, Luca Bertulessi
, Carlo Samori, Salvatore Levantino:
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter. A-SSCC 2021: 1-3 - [c6]Angelo Parisi
, Mario Mercandelli, Carlo Samori, Andrea L. Lacaita
:
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity. ICECS 2021: 1-4 - [c5]Mario Mercandelli
, Alessio Santiccioli, Simone Mattia Dartizio, Abanob Shehata
, Francesco Tesolin, Saleh Karman, Luca Bertulessi
, Francesco Buccoleri, Luca Avallone, Angelo Parisi
, Andrea Leonardo Lacaita
, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino:
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter. ISSCC 2021: 445-447 - [c4]Alessio Santiccioli, Mario Mercandelli
, Simone Mattia Dartizio, Francesco Tesolin, Saleh Karman, Abanob Shehata
, Luca Bertulessi
, Francesco Buccoleri, Luca Avallone, Angelo Parisi
, Dmytro Cherniak, Andrea L. Lacaita
, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino:
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays. ISSCC 2021: 456-458 - 2020
- [b1]Mario Mercandelli:
Techniques for low-jitter and low-area occupation fractional-N Frequency synthesis. Polytechnic University of Milan, Italy, 2020 - [j3]Alessio Santiccioli
, Mario Mercandelli
, Luca Bertulessi
, Angelo Parisi
, Dmytro Cherniak, Andrea L. Lacaita
, Carlo Samori
, Salvatore Levantino
:
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking. IEEE J. Solid State Circuits 55(12): 3349-3361 (2020) - [c3]Alessio Santiccioli, Mario Mercandelli
, Luca Bertulessi
, Angelo Parisi
, Dmytro Cherniak, Andrea Leonardo Lacaita
, Carlo Samori, Salvatore Levantino:
17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking. ISSCC 2020: 268-270 - [c2]Mario Mercandelli
, Alessio Santiccioli, Angelo Parisi
, Luca Bertulessi
, Dmytro Cherniak, Andrea Leonardo Lacaita
, Carlo Samori, Salvatore Levantino:
17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter. ISSCC 2020: 274-276
2010 – 2019
- 2019
- [j2]Alessio Santiccioli
, Mario Mercandelli
, Andrea L. Lacaita
, Carlo Samori
, Salvatore Levantino
:
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power. IEEE J. Solid State Circuits 54(11): 3149-3160 (2019) - [c1]Alessio Santiccioli, Mario Mercandelli
, Andrea L. Lacaita
, Carlo Samori
, Salvatore Levantino:
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power. CICC 2019: 1-4 - 2018
- [j1]Mario Mercandelli
, Luigi Grimaldi
, Luca Bertulessi
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
A Background Calibration Technique to Control the Bandwidth of Digital PLLs. IEEE J. Solid State Circuits 53(11): 3243-3255 (2018)
Coauthor Index
aka: Andrea Leonardo Lacaita
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last updated on 2024-05-08 20:51 CEST by the dblp team
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