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ORCIDYue Niu 0001
Person information
- affiliation: University of Southern California, Los Angeles, CA, USA
- affiliation (former): Northwestern Polytechnical University, School of Electronics and Information, Xi'an, China
Other persons with the same name
- Yue Niu — disambiguation page
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2020 – today
- 2023
[i2]Yue Niu, Rajgopal Kannan, Ajitesh Srivastava, Viktor K. Prasanna:
Reuse Kernels or Activations? A Flexible Dataflow for Low-latency Spectral CNN Acceleration. CoRR abs/2310.10902 (2023)- 2020
- [c5]Yue Niu, Rajgopal Kannan, Ajitesh Srivastava, Viktor K. Prasanna:
Reuse Kernels or Activations?: A Flexible Dataflow for Low-latency Spectral CNN Acceleration. FPGA 2020: 266-276
2010 – 2019
- 2019
- [j1]Wei Zhou
, Yue Niu, Guanwen Zhang:
Sensitivity-Oriented Layer-Wise Acceleration and Compression for Convolutional Neural Network. IEEE Access 7: 38264-38272 (2019) - [c4]Yue Niu, Hanqing Zeng, Ajitesh Srivastava, Kartik Lakhotia, Rajgopal Kannan, Yanzhi Wang, Viktor K. Prasanna:
SPEC2: SPECtral SParsE CNN Accelerator on FPGAs. HiPC 2019: 195-204 - [i1]Yue Niu, Hanqing Zeng, Ajitesh Srivastava, Kartik Lakhotia, Rajgopal Kannan, Yanzhi Wang, Viktor K. Prasanna:
SPEC2: SPECtral SParsE CNN Accelerator on FPGAs. CoRR abs/1910.11103 (2019) - 2017
- [c3]Yue Niu, Zhenyu Liu, Chunsheng Mei, Xiangyang Ji, Wei Zhou, Dongsheng Wang:
Sensitivity-based acceleration and compression algorithm for convolution neural network. GlobalSIP 2017: 769-773 - [c2]Chunsheng Mei, Zhenyu Liu, Yue Niu, Xiangyang Ji, Wei Zhou, Dongsheng Wang:
A 200MHZ 202.4GFLOPS@10.8W VGG16 accelerator in Xilinx VX690T. GlobalSIP 2017: 784-788 - 2016
- [c1]Wei Zhou, Yue Niu, Xiaocong Lian, Xin Zhou, Jiamin Yang:
A Stepped-RAM Reading and Multiplierless VLSI Architecture for Intra Prediction in HEVC. PCM (1) 2016: 469-478
Coauthor Index
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