BibTeX records: Matthew J. P. Walker

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@article{DBLP:journals/trets/MurrayPZWELSGWW20,
  author    = {Kevin E. Murray and
               Oleg Petelin and
               Sheng Zhong and
               Jia Min Wang and
               Mohamed Eldafrawy and
               Jean{-}Philippe Legault and
               Eugene Sha and
               Aaron Graham and
               Jean Wu and
               Matthew J. P. Walker and
               Hanqing Zeng and
               Panagiotis Patros and
               Jason Luu and
               Kenneth B. Kent and
               Vaughn Betz},
  title     = {{VTR} 8: High-performance {CAD} and Customizable {FPGA} Architecture
               Modelling},
  journal   = {{ACM} Trans. Reconfigurable Technol. Syst.},
  volume    = {13},
  number    = {2},
  pages     = {9:1--9:55},
  year      = {2020},
  url       = {https://doi.org/10.1145/3388617},
  doi       = {10.1145/3388617},
  timestamp = {Fri, 10 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/trets/MurrayPZWELSGWW20.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MurrayLWMWHYCKA20,
  author    = {Kevin E. Murray and
               Jason Luu and
               Matthew J. P. Walker and
               Conor McCullough and
               Sen Wang and
               Safeen Huda and
               Bo Yan and
               Charles Chiasson and
               Kenneth B. Kent and
               Jason Helge Anderson and
               Jonathan Rose and
               Vaughn Betz},
  title     = {Optimizing {FPGA} Logic Block Architectures for Arithmetic},
  journal   = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume    = {28},
  number    = {6},
  pages     = {1378--1391},
  year      = {2020},
  url       = {https://doi.org/10.1109/TVLSI.2020.2965772},
  doi       = {10.1109/TVLSI.2020.2965772},
  timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/tvlsi/MurrayLWMWHYCKA20.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2006-09554,
  author    = {Matthew J. P. Walker and
               Bo Yan and
               Yiou Xiao and
               Yafei Wang and
               Ayan Acharya},
  title     = {Isometric Graph Neural Networks},
  journal   = {CoRR},
  volume    = {abs/2006.09554},
  year      = {2020},
  url       = {https://arxiv.org/abs/2006.09554},
  archivePrefix = {arXiv},
  eprint    = {2006.09554},
  timestamp = {Tue, 23 Jun 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/corr/abs-2006-09554.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/WalkerA19,
  author    = {Matthew J. P. Walker and
               Jason Helge Anderson},
  title     = {Generic Connectivity-Based {CGRA} Mapping via Integer Linear Programming},
  booktitle = {27th {IEEE} Annual International Symposium on Field-Programmable Custom
               Computing Machines, {FCCM} 2019, San Diego, CA, USA, April 28 - May
               1, 2019},
  pages     = {65--73},
  publisher = {{IEEE}},
  year      = {2019},
  url       = {https://doi.org/10.1109/FCCM.2019.00019},
  doi       = {10.1109/FCCM.2019.00019},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/conf/fccm/WalkerA19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1901-11129,
  author    = {Matthew J. P. Walker and
               Jason Helge Anderson},
  title     = {Generic Connectivity-Based {CGRA} Mapping via Integer Linear Programming},
  journal   = {CoRR},
  volume    = {abs/1901.11129},
  year      = {2019},
  url       = {http://arxiv.org/abs/1901.11129},
  archivePrefix = {arXiv},
  eprint    = {1901.11129},
  timestamp = {Mon, 04 Feb 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/journals/corr/abs-1901-11129.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/ChinNWYMLA18,
  author    = {S. Alexander Chin and
               Kuang Ping Niu and
               Matthew J. P. Walker and
               Shizhang Yin and
               Alexander Mertens and
               Jongeun Lee and
               Jason Helge Anderson},
  editor    = {Chris Chu and
               Ismail Bustany},
  title     = {Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using
               the Open-Source {CGRA-ME} Framework},
  booktitle = {Proceedings of the 2018 International Symposium on Physical Design,
               {ISPD} 2018, Monterey, CA, USA, March 25-28, 2018},
  pages     = {48--55},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3177540.3177553},
  doi       = {10.1145/3177540.3177553},
  timestamp = {Tue, 05 Feb 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/ispd/ChinNWYMLA18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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