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2020 – today
- 2024
[j3]Hsin-Cheng Lin
, Wei-Teng Hsu, Tsai-Yu Chung, He-Wen Shen, Ching-Wang Yao, Tao Chou, Li-Kai Wang, Chee Wee Liu:
RF Performance Benchmark of Nanosheets, Nanowires, FinFETs, and TreeFETs. IEEE Access 12: 70512-70518 (2024)- 2023
- [c4]Yi-Chun Liu, Yu-Rui Chen, Yun-Wen Chen, Hsin-Cheng Lin, Wan-Hsuan Hsieh, Chien-Te Tu, Bo-Wei Huang, Wei-Jen Chen, Chun-Yi Cheng, Shee-Jier Chueh, Chee Wee Liu:
Extremely High-κ Hf0.2Zr0.8O2 Gate Stacks Integrated into Ge0.95Si0.05 Nanowire and Nanosheet nFETs Featuring Respective Record Ion per Footprint of 9200μA/μm and Record Ion per Stack of 360μA at VOV=VDS=0.5V. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c3]Chung-En Tsai, Chun-Yi Cheng, Bo-Wei Huang, Hsin-Cheng Lin, Tao Chou, Chien-Te Tu, Yi-Chun Liu, Sun-Rong Jan, Yu-Rui Chen, Wan-Hsuan Hsieh, Kung-Ying Chiu, Shee-Jier Chueh, Chee Wee Liu:
Nearly Ideal Subthreshold Swing and Delay Reduction of Stacked Nanosheets Using Ultrathin Bodies. VLSI Technology and Circuits 2022: 401-402
2010 – 2019
- 2013
- [j2]Yu-Fu Yeh, Hsin-Cheng Lin, Chung-Yang Huang:
An Ultrasynchronization Checking Method With Trace-Driven Simulation for Fast and Accurate MPSoC Virtual Platform Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6): 928-939 (2013) - 2012
- [j1]Chih-Lin Hu, Hsin-Cheng Lin, Yu-Feng Hsu, Bing-Jung Hsieh:
A P2P-to-UPnP Proxy Gateway Architecture for Home Multimedia Content Distribution. KSII Trans. Internet Inf. Syst. 6(1): 406-425 (2012) - 2011
- [c2]Yu-Fu Yeh, Chung-Yang Huang, Chi-An Wu, Hsin-Cheng Lin:
Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method. DATE 2011: 353-358
2000 – 2009
- 2005
- [c1]Hsin-Cheng Lin, Szu-Hao Huang, Shang-Hong Lai:
Learning-based video fast-pan detection. ITRE 2005: 181-185
Coauthor Index
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