default search action

combined dblp search
author search
venue search
publication search

ask others

Jerome Quartana

> Home > Persons

Person information

Refine list

refinements active!

zoomed in on ?? of ?? records

view refined list in

export refined list as

showing all ?? records

Conference and Workshop Papers

see FAQ

What is the meaning of the colors in the publication lists?

2006
[c6]
- no documents available
  - no references & citations available
- export record
  dblp key:
  - conf/recosoc/ManetRFJTRQL06
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/recosoc/ManetRFJTRQL06
Pascal Manet, Jean-Baptiste Rigaud, Julien Francq, Marc Jeambrun, Assia Tria, Bruno Robisson, Jerome Quartana, Selma Laabidi:
Integrated Evaluation Platform for Secured Devices. ReCoSoC 2006: 214-219
2005
[c5]
- view
  authority control:
- export record
  dblp key:
  - conf/fpl/QuartanaRBFR05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpl/QuartanaRBFR05
Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin:
GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. FPL 2005: 299-304
[c4]
- no documents available
  - no references & citations available
- export record
  dblp key:
  - conf/recosoc/FesquetQR05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/recosoc/FesquetQR05
Laurent Fesquet, Jerome Quartana, Marc Renaudin:
Asynchronous Systems on Programmable Logic. ReCoSoC 2005: 105-112
[c3]
- view
  - electronic edition via DOI (open access)
  - references & citations
  authority control:
- export record
  dblp key:
  - conf/vlsi/QuartanaFR05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsi/QuartanaFR05
Jerome Quartana, Laurent Fesquet, Marc Renaudin:
Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. VLSI-SoC 2005: 195-207
2002
[c2]
- view
  authority control:
- export record
  dblp key:
  - conf/date/RigaudFRQ02
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/date/RigaudFRQ02
Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana:
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. DATE 2002: 1090
2001
[c1]
- no documents available
  - no references & citations available
- export record
  dblp key:
  - conf/ifip10-5/RigaudQFR01
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ifip10-5/RigaudQFR01
Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin:
Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. VLSI-SOC 2001: 313-324

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.