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Xinlin Geng
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2020 – today
- 2024
- [j3]Zonglin Ye, Xinlin Geng, Yao Xiao, Qian Xie, Zheng Wang:
A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm. IEEE J. Solid State Circuits 59(3): 677-689 (2024) - [c5]Zonglin Ye, Xinlin Geng, Zhixiang Shi, Hongyang Zhang, Qian Xie, Zheng Wang:
A 6.8-to-14.4GHz Octave-Tuning Fractional-N Charge-Pump PLL with Slide-Dithering-Based Background DTC Nonlinearity Calibration for Near-Integer Fractional Spur Mitigation Achieving 78fs RMS Jitter and -258.6dB $\text{FoM}_{\mathrm{T}}$. CICC 2024: 1-2 - 2023
- [j2]Zhenyi Zhang, Maoxuan Yang, Xinlin Geng, Kailei Wang, Qian Xie, Zheng Wang:
A 0.0325-mm² 114-to-147-GHz 6-Bit Passive Vector-Modulated Phase Shifter With MN-Embedded Isolated Power Combiner Achieving <3.7° RMS Phase Error in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 70(11): 4394-4405 (2023) - [c4]Xinlin Geng, Zonglin Ye, Yao Xiao, Oian Xie, Zheng Wang:
A 26GHz Fractional-N Charge-Pump PLL Based on A Dual-DTC-Assisted Time-Amplifying-Phase-Frequency Detector Achieving 37.1fs and 45.6fs rms Jitter for Integer-N and Fractional-N Channels. CICC 2023: 1-2 - [c3]Xinlin Geng, Zonglin Ye, Kailei Wang, Hongyang Zhang, Qian Xie, Zheng Wang:
A Compact Frequency Servo SoC with Background Output Power Calibration for Miniaturized Atomic Clocks. ICTA 2023: 1-2 - 2022
- [c2]Xinlin Geng, Yibo Tian, Yao Xiao, Zonglin Ye, Qian Xie, Zheng Wang:
A 25.8GHz Integer-N PLL With Time-Amplifying Phase-Frequency Detector Achieving 60fsrms Jitter, -252.8dB FoMJ, and Robust Lock Acquisition Performance. ISSCC 2022: 388-390 - 2021
- [j1]Xinlin Geng, Qian Xie, Zheng Wang:
A Quadrature Sub-Sampling Phase Detector for Fast-Relocked Sub-Sampling PLL Under External Interference. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 87-91 (2021)
2010 – 2019
- 2019
- [c1]Xinlin Geng, Qian Xie, Yibo Tian, Yu Duan, Zheng Wang:
The Design of a 28GHz Mixer-Embedded Frequency Shifting PLL in 65nm CMOS with Low In-Band Phase Noise. ISCAS 2019: 1-4
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last updated on 2024-06-04 20:42 CEST by the dblp team
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