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ORCIDAugusto Manuel Marques
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1990 – 1999
- 1999
[j5]Yves Geerts, Augusto Manuel Marques, Michel S. J. Steyaert
, Willy Sansen:
A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications. IEEE J. Solid State Circuits 34(7): 927-936 (1999)- 1998
- [j4]Augusto Manuel Marques, Vincenzo Peluso, Michel S. J. Steyaert, Willy Sansen:
A 15-b resolution 2-MHz Nyquist rate ΔΣ ADC in a 1-μm CMOS technology. IEEE J. Solid State Circuits 33(7): 1065-1075 (1998) - [j3]Vincenzo Peluso, Peter J. Vancorenland, Augusto Manuel Marques, Michel S. J. Steyaert, Willy Sansen:
A 900-mV low-power ΔΣ A/D converter with 77-dB dynamic range. IEEE J. Solid State Circuits 33(12): 1887-1897 (1998) - [j2]José Bastos, Augusto Manuel Marques, Michel S. J. Steyaert, Willy Sansen:
A 12-bit intrinsic accuracy high-speed CMOS DAC. IEEE J. Solid State Circuits 33(12): 1959-1969 (1998) - [j1]Augusto Manuel Marques, Michiel S. J. Steyaert, Willy M. C. Sansen:
Theory of PLL fractional-N frequency synthesizers. Wirel. Networks 4(1): 79-85 (1998) - [c4]Anne Van den Bosch, Marc Borremans, Jan Vandenbussche, Geert Van der Plas, Augusto Manuel Marques, José Bastos, Michiel Steyaert, Georges G. E. Gielen, Willy Sansen:
A 12 bit 200 MHz low glitch CMOS D/A converter. CICC 1998: 249-252 - [c3]Augusto Manuel Marques, José Bastos, Michiel Steyaert, Willy Sansen:
A current steering architecture for 12-bit high-speed D/A converters. ICECS 1998: 23-26 - [c2]Augusto Manuel Marques, Valentino Peluso, Michiel Steyaert, Willy M. C. Sansen:
Analysis of the trade-off between bandwidth, resolution, and power in ΔΣ analog to digital converters. ICECS 1998: 153-156 - [c1]Augusto Manuel Marques, Yves Geerts, Michiel Steyaert, Willy Sansen:
Settling time analysis of third order systems. ICECS 1998: 505-508
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