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Vineesh V. S.

V. S. Vineesh

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2020 – today

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2022
[j2]
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Binod Kumar, V. S. Vineesh, Puneet Nemade, Masahiro Fujita:
Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5709-5721 (2022)
2021
[j1]
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V. S. Vineesh, Binod Kumar, Rushikesh Shinde, Neelam Sharma, Masahiro Fujita, Virendra Singh:
Enhanced Design Debugging With Assistance From Guidance-Based Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(5): 985-998 (2021)
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Harsh Bhargav, Vineesh V. S., Binod Kumar, Virendra Singh:
Enhancing Testbench Quality via Genetic Algorithm. MWSCAS 2021: 652-656
2020
[c5]
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Vinod G. U, Vineesh V. S., Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh:
LUT-based Circuit Approximation with Targeted Error Guarantees. ATS 2020: 1-6
[c4]
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Binod Kumar, Akshay Kumar Jaiswal, V. S. Vineesh, Rushikesh Shinde:
Analyzing Hardware Security Properties of Processors through Model Checking. VLSID 2020: 107-112

2010 – 2019

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2019
[c3]
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Vineesh V. S., Binod Kumar, Rushikesh Shinde, Akshay Jaiswal, Harsh Bhargava, Virendra Singh:
Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification. ATS 2019: 123-128
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V. S. Vineesh, Binod Kumar, Jay Adhaduk:
Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods. VDAT 2019: 413-427
2017
[c1]
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V. S. Vineesh, Nihar Hage, B. Karthik, Virendra Singh:
Achieving full functional coverage for the forwarding unit of pipelined processors. EWDTS 2017: 1-4

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