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ORCIDPrema Kumar Govindaswamy
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Journal Articles
- 2023
[j4]Prema Kumar Govindaswamy, Raviteja Kammari
, Vijaya Sankara Rao Pasupureddi:
An adaptive link training based hybrid circuit topology for full-duplex on-chip interconnects. Int. J. Circuit Theory Appl. 51(8): 3637-3651 (2023)- 2022
- [j3]Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi:
A power-efficient current-integrating hybrid for full-duplex communication over chip-to-chip interconnects. Int. J. Circuit Theory Appl. 50(12): 4219-4233 (2022) - 2021
- [j2]Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi:
A 27-1, 20-Gb/s, Low-Power, Charge-Steering Half-Rate PRBS Generator in 1.2 V, 65 nm CMOS. Circuits Syst. Signal Process. 40(11): 5553-5571 (2021) - 2020
- [j1]Pankaj Venuturupalli, Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi:
Residue monitor enabled charge-mode adaptive echo-cancellation for simultaneous bidirectional signaling over on-chip interconnects. Microelectron. J. 104: 104899 (2020)
Conference and Workshop Papers
- 2024
- [c9]Prema Kumar Govindaswamy, Mursina Khatun, Vijay Shankar Pasupureddi:
A 0.2 pJ/bit, Energy-Efficient, Half-Rate Hybrid Circuit Topology at 6-Gb/s in 1.2V, 65 nm CMOS. ISCAS 2024: 1-5 - [c8]Prema Kumar Govindaswamy, Mursina Khatun, Vijay Shankar Pasupureddi:
A 27-1, 20-Gb/s, 0.1-pJ/b Pseudo Random Bit Sequence Generator Using Incomplete Settling in 1.2V, 65 nm CMOS. ISCAS 2024: 1-5 - [c7]Perakalapudi Ravibabu, Prema Kumar Govindaswamy, Vijay Shankar Pasupureddi:
A 15-Gb/s, 0.036 pJ/bit, Half-Rate, Low Power PRBS Generator in 1.2 V, 65 nm CMOS. ISCAS 2024: 1-5 - [c6]Prema Kumar Govindaswamy, Mursina Khatun, Vijay Shankar Pasupureddi:
A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOS. ISQED 2024: 1-5 - 2023
- [c5]Prema Kumar Govindaswamy, P. Vijay Shankar:
High-Swing, Power-efficient, Current-Mode Hybrid Circuit Topologies for Simultaneous Bidirectional Communication. NEWCAS 2023: 1-5 - 2022
- [c4]Prema Kumar Govindaswamy, Nijwm Wary, Vijaya Sankara Rao Pasupureddi:
Power Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects. ISCAS 2022: 852-856 - [c3]Prema Kumar Govindaswamy, Nijwm Wary, Vijaya Sankara Rao Pasupureddi:
A Low-Power Half-Rate Charge-Steering Hybrid for Full-Duplex Chip-to-Chip Interconnects. ISCAS 2022: 857-861 - 2020
- [c2]Pankaj Venuturupalli, Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi:
An Adaptive Hybrid with Residue Monitor for Full-Duplex On-Chip Interconnects. ISCAS 2020: 1-5 - [c1]Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi:
A 2^7 -1 Low-Power Half-Rate 16-Gb/s Charge-Mode PRBS Generator in 1.2V, 65nm CMOS. ISVLSI 2020: 212-215
Coauthor Index
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