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2020 – today
- 2025
[j5]Rongliang Fu
, Mengmeng Wang, Yirong Kan, Olivia Chen, Nobuyuki Yoshikawa, Bei Yu, Tsung-Yi Ho:
Buffer and Splitter Insertion for Adiabatic Quantum-Flux-Parametron Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(3): 975-988 (2025)- [j4]Rongliang Fu, Chao Wang, Bei Yu, Tsung-Yi Ho:
TeMACLE: A Technology Mapping-Aware Area-Efficient Standard Cell Library Extension Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(8): 3034-3045 (2025) - [j3]Rongliang Fu, Robert Wille, Nobuyuki Yoshikawa, Tsung-Yi Ho:
Efficient Cartesian Genetic Programming-Based Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(9): 3369-3380 (2025) - [c16]Rongliang Fu, Ran Zhang, Ziyang Zheng, Zhengyuan Shi, Yuan Pu, Junying Huang, Qiang Xu, Tsung-Yi Ho:
Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision. DAC 2025: 1-2 - [c15]Wei Xuan, Zhongrui Wang, Lang Feng, Ning Lin, Zihao Xuan, Rongliang Fu, Tsung-Yi Ho, Yuzhong Jiao, Luhong Liang:
SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy. DAC 2025: 1-7 - [c14]Minglei Zhou, Rongliang Fu, Ran Zhang, Xiaochun Ye, Tsung-Yi Ho, Junying Huang:
An Optimal DFF-Oriented Technology Legalization Algorithm for Rapid Single-Flux-Quantum Circuits. ACM Great Lakes Symposium on VLSI 2025: 105-111 - [c13]Yang Su, Sheng Li, Huilong Jiang, Haofei Yin, Rongliang Fu, Junying Huang, Xiaochun Ye, Zhimin Zhang, Jie Ren, Xiaoping Gao, Tsung-Yi Ho, Dongrui Fan:
JBSA: A Bit-Serial Accelerator for Deep Neural Networks Using Superconducting SFQ Logic. ICS 2025: 1092-1105 - [c12]Yuan Pu, Fangzhou Liu, Zhuolun He, Keren Zhu, Rongliang Fu, Ziyi Wang, Tsung-Yi Ho, Bei Yu:
HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning. ISPD 2025: 116-124 - [i1]Wei Xuan, Zhongrui Wang, Lang Feng, Ning Lin, Zihao Xuan, Rongliang Fu, Tsung-Yi Ho, Yuzhong Jiao, Luhong Liang:
SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy. CoRR abs/2508.18924 (2025) - 2024
- [c11]Rongliang Fu, Robert Wille, Tsung-Yi Ho:
RCGP: An Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits based on Efficient Cartesian Genetic Programming. DAC 2024: 219:1-219:6 - [c10]Siyan Chen, Rongliang Fu, Junying Huang, Zhimin Zhang, Xiaochun Ye, Tsung-Yi Ho, Dongrui Fan:
JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits. DATE 2024: 1-6 - [c9]Siyuan Liang, Rongliang Fu, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho:
RABER: Reliability-Aware Bayesian-Optimization-based Control Layer Escape Routing for Flow-based Microfluidics. ICCAD 2024: 159:1-159:9 - [c8]Shui Jiang, Rongliang Fu, Lukas Burgholzer, Robert Wille, Tsung-Yi Ho, Tsung-Wei Huang:
FlatDD: A High-Performance Quantum Circuit Simulator using Decision Diagram and Flat Array. ICPP 2024: 388-399 - 2023
- [c7]Rongliang Fu, Mengmeng Wang, Yirong Kan, Nobuyuki Yoshikawa, Tsung-Yi Ho, Olivia Chen:
A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits. ASP-DAC 2023: 769-774 - [c6]Rongliang Fu, Junying Huang, Mengmeng Wang, Nobuyuki Yoshikawa, Bei Yu, Tsung-Yi Ho, Olivia Chen:
BOMIG: A Majority Logic Synthesis Framework for AQFP Logic. DATE 2023: 1-2 - [c5]Xinda Chen, Rongliang Fu, Junying Huang, Huawei Cao, Zhimin Zhang, Xiaochun Ye, Tsung-Yi Ho, Dongrui Fan:
JRouter: A Multi-Terminal Hierarchical Length-Matching Router under Planar Manhattan Routing Model for RSFQ Circuits. ACM Great Lakes Symposium on VLSI 2023: 515-520 - [c4]Rongliang Fu, Olivia Chen, Nobuyuki Yoshikawa, Tsung-Yi Ho:
Exact Logic Synthesis for Reversible Quantum-Flux-Parametron Logic. ICCAD 2023: 1-9 - [c3]Rongliang Fu, Olivia Chen, Bei Yu, Nobuyuki Yoshikawa, Tsung-Yi Ho:
DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits. ICCAD 2023: 1-8 - 2022
- [j2]Junying Huang, Rongliang Fu, Xiaochun Ye, Dongrui Fan:
A survey on superconducting computing technology: circuits, architectures and design tools. CCF Trans. High Perform. Comput. 4(1): 1-22 (2022) - [j1]Rongliang Fu, Junying Huang, Haibin Wu, Xiaochun Ye, Dongrui Fan, Tsung-Yi Ho:
JBNN: A Hardware Design for Binarized Neural Networks Using Single-Flux-Quantum Circuits. IEEE Trans. Computers 71(12): 3203-3214 (2022) - 2021
- [c2]Rongliang Fu, Junying Huang, Zhimin Zhang:
Equivalence Checking for Superconducting RSFQ Logic Circuits. ACM Great Lakes Symposium on VLSI 2021: 51-56 - 2020
- [c1]Rongliang Fu, Zhimin Zhang, Guang-Ming Tang, Junying Huang, Xiaochun Ye, Dongrui Fan, Ninghui Sun:
Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits. ACM Great Lakes Symposium on VLSI 2020: 145-150
Coauthor Index
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