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ORCIDNirnjan M. Devashrayee
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2010 – 2019
- 2018
[j5]Vijay Savani, N. M. Devashrayee:
Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator. Microelectron. J. 74: 116-126 (2018)- 2015
- [c10]Vijay Savani
, N. M. Devashrayee:
Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology. VDAT 2015: 1-2 - [c9]Rakesh Trivedi, N. M. Devashrayee, Usha Sandeep Mehta, N. M. Desai, Himanshu Patel:
Development of Radiation Hardened by Design(RHBD) primitive gates using 0.18μm CMOS technology. VDAT 2015: 1-2 - 2011
- [j4]Usha Sandeep Mehta, Kankar S. Dasgupta, Nirnjan M. Devashrayee:
Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method. VLSI Design 2011: 756561:1-756561:8 (2011) - [j3]Usha Sandeep Mehta, Kankar S. Dasgupta, Niranjan M. Devashrayee:
Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey. VLSI Design 2011: 948926:1-948926:7 (2011) - [c8]A. P. Naik, N. M. Devashrayee:
A novel OTA and FVF based second generation current conveyor. ICWET 2011: 1044-1048 - 2010
- [j2]Usha Sandeep Mehta, Kankar S. Dasgupta, Nirnjan M. Devashrayee:
Modified Selective Huffman Coding for Optimization of Test Data Compression, Test Application Time and Area Overhead. J. Electron. Test. 26(6): 679-688 (2010) - [j1]Usha Sandeep Mehta, Kankar S. Dasgupta, Niranjan M. Devashrayee:
Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds? - A Survey. VLSI Design 2010: 670476:1-670476:9 (2010) - [c7]Usha Sandeep Mehta, Kankar S. Dasgupta, Niranjan M. Devashrayee:
Combining unspecified test data bit filling methods and run length based codes to estimate compression, power and area overhead. APCCAS 2010: 40-43 - [c6]Shruti Oza, N. M. Devashrayee:
Low voltage, high folding rate folding amplifier. ICWET 2010: 899-902 - [c5]Usha Sandeep Mehta, Niranjan M. Devashrayee, Kankar S. Dasgupta:
Hamming Distance Based 2-D Reordering with Power Efficient Don't Care Bit Filling: Optimizing the test data compression method. SoC 2010: 1-7 - [c4]Usha Sandeep Mehta, Niranjan M. Devashrayee, Kankar S. Dasgupta:
Combining Unspecified Test Data Bit Filling Methods and Run Length Based Codes to Estimate Compression, Power and Area Overhead. ISVLSI 2010: 448-449 - [c3]Usha Sandeep Mehta, Kankar S. Dasgupta, Nirnjan M. Devashrayee:
Hamming Distance Based Reordering and Columnwise Bit Stuffing with Difference Vector: A Better Scheme for Test Data Compression with Run Length Based Codes. VLSI Design 2010: 33-38
2000 – 2009
- 2009
- [c2]Shruti Oza, N. M. Devashrayee:
Low Voltage, Low Power Folding Amplifier for Folding & Interpolating ADC. ARTCom 2009: 178-182 - [c1]Usha Sandeep Mehta, Kankar S. Dasgupta, Nirnjan M. Devashrayee:
Survey of Test Data Compression Technique Emphasizing Code Based Schemes. DSD 2009: 617-620
Coauthor Index
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