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Xuguang Guan
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2010 – 2019
- 2017
- [c7]Jia-Wei Ma, Xuguang Guan, Tong Zhou, Tao Sun:
A new countermeasure against side channel attack for HMAC-SM3 hardware. ASICON 2017: 327-330 - [c6]Yong Gu, Xuguang Guan, Tong Zhou:
The configurable current flattening circuit for DPA countermeasures. ASICON 2017: 410-413 - 2016
- [c5]Xinyu Chen, Yong Gu, Chenxu Wang, Xuguang Guan:
Asymmetric multiprocessing for motion control based on Zynq SoC. FPT 2016: 315-318 - 2010
- [j1]Xuguang Guan, Zhangming Zhu, Duan Zhou, Yintang Yang:
High Speed Multi-Resource Arbiter with Active Virtual Channel Allocation for Network on Chips. J. Circuits Syst. Comput. 19(7): 1579-1596 (2010) - [c4]Xuguang Guan, Yu Liu, Yintang Yang:
Performance Analysis of Low Power Null Convention Logic Units with Power Cutoff. APWCS 2010: 55-58 - [c3]Yu Liu, Xuguang Guan, Yang Yang, Yintang Yang:
An asynchronous low latency ordered arbiter for network on chips. ICNC 2010: 962-966
2000 – 2009
- 2009
- [c2]Xuguang Guan, Duan Zhou, Yintang Yang, Zhangming Zhu:
A GALS Delay-insensitive Self-timed Wrapper for Network on Chips. PACCS 2009: 265-268 - [c1]Xuguang Guan, Duan Zhou, Dan Wang, Yintang Yang, Zhangming Zhu:
A Novel GALS Single-Track Protocol Asynchronous Communication Circuits. PACCS 2009: 269-272
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last updated on 2024-04-25 05:52 CEST by the dblp team
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