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Yalçin Balcioglu
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2010 – 2019
- 2017
- [j2]Yalçin Balcioglu, Günhan Dündar:
A 0.65-1.35 GHz synthesizable all-digital phase locked loop with quantization noise suppressing time-to-digital converter. Turkish J. Electr. Eng. Comput. Sci. 25: 2410-2423 (2017) - [j1]Yalçin Balcioglu, Günhan Dündar:
A standard cell phase locked loop design, analysis and high-level synthesis tool (CellPLL). Integr. 58: 142-154 (2017) - 2015
- [c4]Yalçin Balcioglu, Günhan Dündar:
A synthesizable Time to Digital Converter (TDC) with MIMO spatial oversampling method. NEWCAS 2015: 1-4 - [c3]Yalçin Balcioglu, Günhan Dündar:
Improved standard cell synthesizable Digitally Controlled Oscillator. SIU 2015: 355-358
2000 – 2009
- 2009
- [c2]Yalçin Balcioglu, Füsun Özgüner, Ümit Özgüner, Keith A. Redmill:
A multiple intersection integrated wireless and vehicular network simulator. VNC 2009: 1-5 - 2008
- [c1]Boangoat Jarupan, Yalçin Balcioglu, Eylem Ekici, Füsun Özgüner, Ümit Özgüner:
An Integrated Wireless Intersection Simulator for collision warning systems in vehicular networks. ICVES 2008: 340-345
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