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ORCIDSasi Kumar Arunachalam
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2010 – 2019
- 2014
[j5]Xicheng Jiang, Jungwoo Song, Darwin Cheung, Minsheng Wang, Sasi Kumar Arunachalam:
Integrated Class-D Audio Amplifier With 95% Efficiency and 105 dB SNR. IEEE J. Solid State Circuits 49(11): 2387-2396 (2014)- [c5]Zhengyu Wang, Tay Hui Zheng, Dongtian Lu, Sasi Kumar Arunachalam, Xicheng Jiang:
Configurable incremental sigma-delta ADC for DC measure and audio conversion. CICC 2014: 1-4 - 2013
- [j4]Xicheng Jiang, Jungwoo Song, Minsheng Wang, Jianlong Chen, Sasi Kumar Arunachalam:
Integrated Pop-Click Noise Suppression, EMI Reduction, and Short-Circuit Detection for Class-D Audio Amplifiers. IEEE J. Solid State Circuits 48(4): 1099-1108 (2013) - [c4]Jianlong Chen, Sasi Kumar Arunachalam, Todd Brooks, Iuri Mehr, Felix Cheung, Hariprasath Venkatram:
A 62mW stereo class-G headphone driver with 108dB dynamic range and 600µA/channel quiescent current. ISSCC 2013: 182-183 - 2012
- [c3]Xicheng Jiang, Jungwoo Song, Minsheng Wang, Jianlong Chen, Sasi Kumar Arunachalam, Todd L. Brooks:
Circuit techniques to overcome Class-D audio amplifier limitations in mobile devices. VLSIC 2012: 18-19 - 2010
- [c2]Sherif Galal, Jurgen van Engelen, Jared Welz, Henrik Jensen, Khaled Abdelfattah, Felix Cheung, Sasi Kumar Arunachalam, Xicheng Jiang, Todd Brooks:
A 32-channel front-end for wireless HID using inverse-STF pre-filtering technique. CICC 2010: 1-4
2000 – 2009
- 2006
- [j3]Patrick Birrer, Sasi Kumar Arunachalam, Martin Held, Kartikeya Mayaram, Terri S. Fiez:
Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12): 2578-2587 (2006) - 2005
- [j2]Brian E. Owens, Sirisha Adluri, Patrick Birrer, Robert Shreeve, Sasi Kumar Arunachalam, Kartikeya Mayaram, Terri S. Fiez:
Simulation and measurement of supply and substrate noise in mixed-signal ICs. IEEE J. Solid State Circuits 40(2): 382-391 (2005) - [j1]Ajit Sharma, Patrick Birrer, Sasi Kumar Arunachalam, Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver. IEEE Trans. Very Large Scale Integr. Syst. 13(7): 843-851 (2005) - 2003
- [c1]Brian E. Owens, Patrick Birrer, Sirisha Adluri, Robert Shreeve, Sasi Kumar Arunachalam, Husni Habal, Shu-Ching Hsu, Ajit Sharma, Kartikeya Mayaram, Terri S. Fiez:
Strategies for simulation, measurement and suppression of digital noise in mixed-signal circuits. CICC 2003: 361-364
Coauthor Index
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