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ORCIDBapiraju Vinnakota
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- affiliation: Lawrence Berkeley National Laboratory, Berkeley, CA, USA
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2020 – today
- 2023
[j21]Bapi Vinnakota
, John M. Shalf:
Modular High-Performance Computing Using Chiplets. Comput. Sci. Eng. 25(6): 39-48 (2023)- [c47]Bapi Vinnakota, Jaber Derakhshandeh, Eric Beyne, Erik Jan Marinissen, Sreejit Chakravarty:
IP Session on Chiplet: Design, Assembly, and Test. VTS 2023: 1 - 2022
- [c46]Vivek Raghunathan, Karl Muth, Bapiraju Vinnakota, Prasad Venugopal, Rebecca Schaevitz, Manish Mehta:
SCIP to the Next Generation of Computing: Extending More than Moore with Silicon Photonics Chiplets in Package (SCIP). ISQED 2022: 1-6 - 2021
- [j20]Bapiraju Vinnakota, Ishwar Agarwal, Kevin Drucker, Dharmesh Jani, Gary Miller, Millind Mittal, Robert Wang:
The Open Domain-Specific Architecture. IEEE Micro 41(1): 30-36 (2021) - [j19]Shahab Ardalan, Ramin Farjadrad, Mark Kuemerle, Ken Poulton, Suresh Subramaniam, Bapiraju Vinnakota:
An Open Inter-Chiplet Communication Link: Bunch of Wires (BoW). IEEE Micro 41(1): 54-60 (2021) - [c45]Bapiraju Vinnakota:
The Open Domain-Specific Architecture: Next Steps to Production. NANOCOM 2021: 19:1-19:5 - [c44]Bapi Vinnakota:
The Open Domain-Specific Architecture: An Introduction (Invited). SLIP 2021: 43 - 2020
- [j18]Ramin Farjadrad, Mark Kuemerle, Bapi Vinnakota:
A Bunch-of-Wires (BoW) Interface for Interchiplet Communication. IEEE Micro 40(1): 15-24 (2020) - [c43]Shahab Ardalan, Halil Cirit, Ramin Farjad-Rad, Mark Kuemerle, Ken Poulton, Suresh Subramanian, Bapiraju Vinnakota:
Bunch of Wires: An Open Die-to-Die Interface. Hot Interconnects 2020: 9-16 - [c42]Kevin Drucker, Dharmesh Jani, Ishwar Agarwal, Gary Miller, Millind Mittal, Robert Wang, Bapiraju Vinnakota:
The Open Domain-Specific Architecture. Hot Interconnects 2020: 25-32 - [c41]Marc Hutner, R. Sethuram, Bapi Vinnakota, Dave Armstrong, A. Copperhall:
Special Session: Test Challenges in a Chiplet Marketplace. VTS 2020: 1-12
2010 – 2019
- 2019
- [c40]Greg Taylor, Ramin Farjadrad, Bapiraju Vinnakota:
High Capacity On-Package Physical Link Considerations. Hot Interconnects 2019: 19-22 - [c39]Ramin Farjadrad, Bapiraju Vinnakota:
A Bunch of Wires (BoW) Interface for Inter-Chiplet Communication. Hot Interconnects 2019: 27-273 - 2010
- [c38]Mehdi Baradaran Tahoori, Ishwar Parulkar, Dan Alexandrescu, Kevin Granlund, Allan Silburt, Bapi Vinnakota:
Panel: Reliability of data centers: Hardware vs. software. DATE 2010: 1620
2000 – 2009
- 2009
- [j17]Amit P. Jardosh, Konstantina Papagiannaki, Elizabeth M. Belding, Kevin C. Almeroth, Gianluca Iannaccone, Bapi Vinnakota:
Green WLANs: On-Demand WLAN Infrastructures. Mob. Networks Appl. 14(6): 798-814 (2009) - 2007
- [c37]Amit P. Jardosh, Gianluca Iannaccone, Konstantina Papagiannaki, Bapi Vinnakota:
Towards an Energy-Star WLAN Infrastructure. HotMobile 2007: 85-90 - 2004
- [c36]Wooyoung Choi, Bapiraju Vinnakota, Ramesh Harjani:
A digital DFT technique for verifying the static performance of A/D converters. CICC 2004: 207-210 - [c35]Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota:
Combining dictionary coding and LFSR reseeding for test data compression. DAC 2004: 944-947 - 2003
- [c34]Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota:
Test Vector Generation Based on Correlation Model for Ratio-Iddq. ITC 2003: 545-554 - [c33]Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota:
Development of Energy Consumption Ratio Test. VTS 2003: 279-286 - 2002
- [j16]Wanli Jiang, Bapiraju Vinnakota:
Statistical threshold formulation for dynamic Idd test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(6): 694-705 (2002) - 2001
- [j15]Wanli Jiang, Bapiraju Vinnakota:
Defect-oriented test scheduling. IEEE Trans. Very Large Scale Integr. Syst. 9(3): 427-438 (2001) - [c32]Xiaoyun Sun, Seonki Kim, Bapiraju Vinnakota:
Crosstalk Fault Detection by Dynamic Idd. ICCAD 2001: 375- - [c31]Amit K. Varshney, Bapiraju Vinnakota, Eric Skuldt, Brion L. Keller:
High Performance Parallel Fault Simulation. ICCD 2001: 308-313 - [c30]Wooyoung Choi, Ramesh Harjani, Bapiraju Vinnakota:
Non-ideal amplifier effects on the accuracy of analog-to-digital capacitor ratio converter. ISCAS (1) 2001: 552-555 - [c29]Xiaoyun Sun, Bapiraju Vinnakota:
Current Measurement for Dynamic Idd Test. VTS 2001: 117-123 - 2000
- [j14]Wanli Jiang, Bapiraju Vinnakota:
IC test using the energy consumption ratio. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1): 129-141 (2000) - [j13]Bapiraju Vinnakota, Ramesh Harjani:
DFT for digital detection of analog parametric faults in SC filters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(7): 789-798 (2000) - [c28]Wooyoung Choi, Ramesh Harjani, Bapiraju Vinnakota:
Optimal test-set generation for parametric fault detection in switched capacitor filters. Asian Test Symposium 2000: 72-77 - [c27]Seonki Kim, Bapiraju Vinnakota:
Fast Test Application Technique Without Fast Scan Clocks. ICCAD 2000: 464-467 - [c26]Seonki Kim, Sreejit Chakravarty, Bapiraju Vinnakota:
An analysis of the delay defect detection capability of the ECR test method. ITC 2000: 1060-1069 - [c25]Bapiraju Vinnakota, André Ivanov:
Biomedical ICs: What is Different about Testing those ICs? VTS 2000: 329-332
1990 – 1999
- 1999
- [j12]Minesh B. Amin, Bapiraju Vinnakota:
Data parallel fault simulation. IEEE Trans. Very Large Scale Integr. Syst. 7(2): 183-190 (1999) - [c24]Bapiraju Vinnakota, Ramesh Harjani:
Digital detection of parametric faults in data converters. CICC 1999: 151-154 - [c23]Ramesh Harjani, Bapiraju Vinnakota:
Digital Aetection of Analog Parametric Faults in SC Filters. DAC 1999: 772-777 - [c22]Wanli Jiang, Bapiraju Vinnakota:
IC Test Using the Energy Consumption Ratio. DAC 1999: 976-981 - [c21]Bapiraju Vinnakota:
Deep submicron defect detection with the energy consumption ratio. ICCAD 1999: 467-470 - [c20]Wanli Jiang, Bapiraju Vinnakota:
Statistical threshold formulation for dynamic I_dd test. ITC 1999: 57-66 - [c19]Wanli Jiang, Bapiraju Vinnakota:
Defect-Oriented Test Scheduling. VTS 1999: 433-439 - 1998
- [j11]Bapiraju Vinnakota, Jason Andrews:
Fast fault translation. IEEE Trans. Very Large Scale Integr. Syst. 6(1): 122-133 (1998) - [c18]Dechang Sun, Bapiraju Vinnakota, Wanli Jiang:
Fast State Verification. DAC 1998: 619-624 - [c17]Bapiraju Vinnakota, Wanli Jiang, Dechang Sun:
Process-tolerant test with energy consumption ratio. ITC 1998: 1027-1036 - 1997
- [j10]Minesh B. Amin, Bapiraju Vinnakota:
Workload Distribution in Fault Simulation. J. Electron. Test. 10(3): 277-282 (1997) - [j9]Bapiraju Vinnakota:
Monitoring Power Dissipation for Fault Detection. J. Electron. Test. 11(2): 173-181 (1997) - [c16]Bapiraju Vinnakota, Ramesh Harjani, Wooyoung Choi:
Pseudoduplication - An ACOB Technique for Single-Ended Circuits. VLSI Design 1997: 398-402 - 1996
- [j8]Nicholas J. Stessman, Bapiraju Vinnakota, Ramesh Harjani:
System-level design for test of fully differential analog circuits. IEEE J. Solid State Circuits 31(10): 1526-1534 (1996) - [c15]Minesh B. Amin, Bapiraju Vinnakota:
Zamlog: a parallel algorithm for fault simulation based on Zambezi. ICCAD 1996: 509-512 - [c14]Bapiraju Vinnakota, Ramesh Harjani:
Mixed-Signal Design for Test. VLSI Design 1996: 2 - [c13]Minesh B. Amin, Bapiraju Vinnakota:
ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator. VTS 1996: 438-443 - [c12]Bapiraju Vinnakota:
Monitoring power dissipation for fault detection. VTS 1996: 483-488 - 1995
- [j7]Bapiraju Vinnakota:
Implementing Multiplication with Split Read-Only Memory. IEEE Trans. Computers 44(11): 1352-1356 (1995) - [c11]Bapiraju Vinnakota, Ramesh Harjani, Nicholas J. Stessman:
System-Level Design for Test of Fully Differential Analog Circuits. DAC 1995: 450-454 - [c10]Minesh B. Amin, Bapiraju Vinnakota:
Data parallel fault simulation. ICCD 1995: 610-615 - [c9]Bapiraju Vinnakota, Nicholas J. Stessman:
Reducing test application time in scan design schemes. VTS 1995: 367-373 - 1994
- [j6]Bapiraju Vinnakota, V. V. Bapeswara Rao:
Enumeration of Binary Trees. Inf. Process. Lett. 51(3): 125-127 (1994) - [j5]Bapiraju Vinnakota, V. V. Bapeswara Rao:
Generation of All Reed-Muller Expansions of a Switching Function. IEEE Trans. Computers 43(1): 122-124 (1994) - [j4]Bapiraju Vinnakota, Niraj K. Jha:
Design of Algorithm-Based Fault-Tolerant Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. IEEE Trans. Parallel Distributed Syst. 5(10): 1099-1106 (1994) - [j3]Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi:
A C-testable carry-free divider. IEEE Trans. Very Large Scale Integr. Syst. 2(4): 472-488 (1994) - [c8]Bapiraju Vinnakota, Jason Andrews:
Functional Test Generation for FSMs by Fault Extraction. DAC 1994: 712-715 - [c7]Bapiraju Vinnakota, Ramesh Harjani:
The Design of Analog Self-Checking Circuits. VLSI Design 1994: 67-70 - [c6]Ramesh Harjani, Bapiraju Vinnakota:
Analog circuit observer blocks. VTS 1994: 258-263 - 1993
- [j2]Bapiraju Vinnakota, Niraj K. Jha:
Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems. IEEE Trans. Computers 42(8): 924-937 (1993) - [j1]Bapiraju Vinnakota, Niraj K. Jha:
Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs. IEEE Trans. Parallel Distributed Syst. 4(8): 864-874 (1993) - [c5]Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi:
A C-Testable Carry-Free Divider. ICCD 1993: 206-213 - 1992
- [c4]Bapiraju Vinnakota, Jason Andrews:
Repair of RAMs With Clustered Faults. ICCD 1992: 582-585 - 1991
- [c3]Bapiraju Vinnakota, Niraj K. Jha:
MACHETE: synthesis of sequential machines for easy testability. EURO-DAC 1991: 289-293 - [c2]Bapiraju Vinnakota, Niraj K. Jha:
Design of Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. FTCS 1991: 504-511 - 1990
- [c1]Bapiraju Vinnakota, Niraj K. Jha:
A dependence graph-based approach to the design of algorithm-based fault tolerant systems. FTCS 1990: 122-129
Coauthor Index
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