
BibTeX records: Veynu Narasiman
@inproceedings{DBLP:conf/sbac-pad/AlvesKENVNP12, author = {Marco A. Z. Alves and Khubaib and Eiman Ebrahimi and Veynu Narasiman and Carlos Villavieja and Philippe Olivier Alexandre Navaux and Yale N. Patt}, editor = {Jairo Panetta and Jos{\'{e}} E. Moreira and David A. Padua and Philippe O. A. Navaux}, title = {Energy Savings via Dead Sub-Block Prediction}, booktitle = {{IEEE} 24th International Symposium on Computer Architecture and High Performance Computing, {SBAC-PAD} 2012, New York, NY, USA, October 24-26, 2012}, pages = {51--58}, publisher = {{IEEE} Computer Society}, year = {2012}, url = {https://doi.org/10.1109/SBAC-PAD.2012.30}, doi = {10.1109/SBAC-PAD.2012.30}, timestamp = {Fri, 09 Apr 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/sbac-pad/AlvesKENVNP12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tc/LeeMNP11, author = {Chang Joo Lee and Onur Mutlu and Veynu Narasiman and Yale N. Patt}, title = {Prefetch-Aware Memory Controllers}, journal = {{IEEE} Trans. Computers}, volume = {60}, number = {10}, pages = {1406--1430}, year = {2011}, url = {https://doi.org/10.1109/TC.2010.214}, doi = {10.1109/TC.2010.214}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tc/LeeMNP11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/NarasimanSLMMP11, author = {Veynu Narasiman and Michael Shebanow and Chang Joo Lee and Rustam Miftakhutdinov and Onur Mutlu and Yale N. Patt}, editor = {Carlo Galuzzi and Luigi Carro and Andreas Moshovos and Milos Prvulovic}, title = {Improving {GPU} performance via large warps and two-level warp scheduling}, booktitle = {44rd Annual {IEEE/ACM} International Symposium on Microarchitecture, {MICRO} 2011, Porto Alegre, Brazil, December 3-7, 2011}, pages = {308--317}, publisher = {{ACM}}, year = {2011}, url = {https://doi.org/10.1145/2155620.2155656}, doi = {10.1145/2155620.2155656}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/micro/NarasimanSLMMP11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/LeeNMP09, author = {Chang Joo Lee and Veynu Narasiman and Onur Mutlu and Yale N. Patt}, editor = {David H. Albonesi and Margaret Martonosi and David I. August and Jos{\'{e}} F. Mart{\'{\i}}nez}, title = {Improving memory bank-level parallelism in the presence of prefetching}, booktitle = {42st Annual {IEEE/ACM} International Symposium on Microarchitecture {(MICRO-42} 2009), December 12-16, 2009, New York, New York, {USA}}, pages = {327--336}, publisher = {{ACM}}, year = {2009}, url = {https://doi.org/10.1145/1669112.1669155}, doi = {10.1145/1669112.1669155}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/micro/LeeNMP09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/LeeMNP08, author = {Chang Joo Lee and Onur Mutlu and Veynu Narasiman and Yale N. Patt}, title = {Prefetch-Aware {DRAM} Controllers}, booktitle = {41st Annual {IEEE/ACM} International Symposium on Microarchitecture {(MICRO-41} 2008), November 8-12, 2008, Lake Como, Italy}, pages = {200--209}, publisher = {{IEEE} Computer Society}, year = {2008}, url = {https://doi.org/10.1109/MICRO.2008.4771791}, doi = {10.1109/MICRO.2008.4771791}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/micro/LeeMNP08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }

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