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Sandeep K. Gupta

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This is just a disambiguation page, and is not intended to be the bibliography of an actual person. The links to all actual bibliographies of persons of the same or a similar name can be found below. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.

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2000 – 2009

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2009
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Carlos Cordeiro, Romano Fantacci, Sandeep K. Gupta, Joseph A. Paradiso, Asim Smailagic, Mani B. Srivastava:
Body Area Networking: Technology and Applications. IEEE J. Sel. Areas Commun. 27(1): 1-4 (2009)
2007
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Hugo Cheung, Sandeep K. Gupta:
Accurate modeling and fault simulation of Byzantine resistive bridges. ICCD 2007: 347-353
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Shideh Shahidi, Sandeep K. Gupta:
ERTG: A test generator for error-rate testing. ITC 2007: 1-10
2006
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Shideh Shahidi, Sandeep K. Gupta:
Estimating Error Rate during Self-Test via One's Counting. ITC 2006: 1-9

1990 – 1999

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1998
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Chih-Ang Chen, Sandeep K. Gupta:
Efficient BIST TPG design and test set compaction via input reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8): 692-705 (1998)
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Chih-Ang Chen, Sandeep K. Gupta:
Efficient BIST TPG design and test set compaction for delay testing via input reduction. ICCD 1998: 32-39
1996
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Chih-Ang Chen, Sandeep K. Gupta:
Design of efficient BIST test pattern generators for delay testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1568-1575 (1996)
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Hugo Cheung, Sandeep K. Gupta:
A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation. ITC 1996: 386-395
1995
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Mody Lempel, Sandeep K. Gupta:
Zero Aliasing for Modeled Faults. IEEE Trans. Computers 44(11): 1283-1295 (1995)
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Chih-Ang Chen, Sandeep K. Gupta:
A Methodology to Design Efficient BIST Test Pattern Generators. ITC 1995: 814-823

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