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Héctor Pettenghi
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2020 – today
- 2024
- [c15]Gabriel Fernandes, Augusto Vassoler, Eduardo Bezerra, Leonel Sousa, Héctor Pettenghi:
A Comprehensive Approach and Analysis of Reverse Converters for a Class of Moduli Sets. LASCAS 2024: 1-5 - 2023
- [j12]Vanessa Prediger, Fábio Bairros, Laio Oriel Seman
, Eduardo Augusto Bezerra, Héctor Pettenghi:
RNS processor using moduli sets of the form 2n±1. Int. J. Circuit Theory Appl. 51(7): 3432-3442 (2023) - 2020
- [j11]Leonel Sousa
, Rogerio Paludo, Paulo Martins
, Héctor Pettenghi
:
Towards the Integration of Reverse Converters into the RNS Channels. IEEE Trans. Computers 69(3): 342-348 (2020)
2010 – 2019
- 2019
- [c14]Fabián Leonardo Cabrera
, Fernando Rangel de Sousa, Héctor Pettenghi
:
Introducing Asymmetry in a CMOS Latch to Obtain Inherent Power-On-Reset Behavior. LASCAS 2019: 61-64 - 2018
- [j10]Héctor Pettenghi
, Rogerio Paludo
, Roberto de Matos, Pavel Alekseevich Lyakhov
:
Efficient RNS Reverse Converters for Moduli Sets with Dynamic Ranges Up to \((10n+1)\) -bit. Circuits Syst. Signal Process. 37(11): 5178-5196 (2018) - 2017
- [c13]Roberto de Matos, Rogerio Paludo, Nikolay I. Chervyakov
, Pavel Alekseevich Lyakhov
, Héctor Pettenghi
:
Efficient implementation of modular multiplication by constants applied to RNS reverse converters. ISCAS 2017: 1-4 - 2016
- [j9]Héctor Pettenghi
, Ricardo Chaves
, Roberto de Matos, Leonel Sousa
:
Method for designing two levels RNS reverse converters for large dynamic ranges. Integr. 55: 22-29 (2016) - [c12]Héctor Pettenghi
, Roberto de Matos, Amir Sabbagh Molahosseini
:
RNS reverse converters for moduli sets with dynamic ranges of 9n-bit. LASCAS 2016: 143-146 - 2015
- [c11]Héctor Pettenghi
, Leonel Sousa
:
RNS reverse converters based on the new Chinese Remainder Theorem I. ISCAS 2015: 830-833 - 2014
- [j8]Héctor Pettenghi
, Frederico Pratas, Leonel Sousa
:
Method for Designing Efficient Mixed Radix Multipliers. Circuits Syst. Signal Process. 33(10): 3165-3193 (2014) - [j7]Héctor Pettenghi
, Sorin Cotofana
, Leonel Sousa
:
Efficient Method for Designing Modulo {2n ± k} Multipliers. J. Circuits Syst. Comput. 23(1) (2014) - [c10]Héctor Pettenghi
, Jude Angelo Ambrose, Ricardo Chaves
, Leonel Sousa
:
Method for designing multi-channel RNS architectures to prevent power analysis SCA. ISCAS 2014: 2233-2236 - 2013
- [j6]Jude Angelo Ambrose, Héctor Pettenghi
, Darshana Jayasinghe, Leonel Sousa:
Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks. IET Circuits Devices Syst. 7(5): 283-293 (2013) - [j5]Héctor Pettenghi
, Ricardo Chaves
, Leonel Sousa
:
RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to (8n+1)-bit. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(6): 1487-1500 (2013) - [j4]Héctor Pettenghi
, Ricardo Chaves
, Leonel Sousa
:
Method to Design General RNS Reverse Converters for Extended Moduli Sets. IEEE Trans. Circuits Syst. II Express Briefs 60-II(12): 877-881 (2013) - [c9]Jude Angelo Ambrose, Héctor Pettenghi
, Leonel Sousa
:
DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks. ASP-DAC 2013: 620-625 - 2012
- [c8]Héctor Pettenghi
, Leonel Sousa
, Jude Angelo Ambrose:
Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion. ASP-DAC 2012: 819-824 - [c7]Pedro Miguens Matutino
, Héctor Pettenghi
, Ricardo Chaves
, Leonel Sousa
:
RNS Arithmetic Units for Modulo {2^n+-k}. DSD 2012: 795-802 - 2010
- [c6]Héctor Pettenghi
, Ricardo Chaves
, Leonel Sousa
, Maria J. Avedillo
:
An improved RNS generator 2n +/- k based on threshold logic. VLSI-SoC 2010: 119-124
2000 – 2009
- 2009
- [j3]José M. Quintana
, Maria J. Avedillo
, Juan Núñez
, Héctor Pettenghi
:
Operation Limits for RTD-Based MOBILE Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(2): 350-363 (2009) - 2008
- [j2]Héctor Pettenghi
, Maria J. Avedillo
, José M. Quintana
:
Using multi-threshold threshold gates in RTD-based logic design: A case study. Microelectron. J. 39(2): 241-247 (2008) - [c5]Héctor Pettenghi
, Maria J. Avedillo
, José M. Quintana
:
A novel contribution to the RTD-based threshold logic family. ISCAS 2008: 2350-2353 - 2007
- [c4]Héctor Pettenghi
, Maria J. Avedillo, José M. Quintana:
Non Return Mobile Logic Family. ISCAS 2007: 125-128 - 2006
- [j1]Maria J. Avedillo
, José M. Quintana
, Héctor Pettenghi Roldán
:
Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors. IEEE Trans. Circuits Syst. II Express Briefs 53-II(5): 334-338 (2006) - [c3]José M. Quintana, Maria J. Avedillo, Héctor Pettenghi:
Self-latching operation limits for MOBILE circuits. ISCAS 2006 - 2005
- [c2]Maria J. Avedillo
, José M. Quintana
, Héctor Pettenghi
:
Logic Models Supporting the Design of MOBILE-based RTD Circuits. ASAP 2005: 254-259 - 2004
- [c1]José M. Quintana, Maria J. Avedillo, Héctor Pettenghi:
Programmable logic gate based on resonant tunnelling devices. ISCAS (3) 2004: 697-700
Coauthor Index
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last updated on 2024-05-09 23:55 CEST by the dblp team
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