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Jian Luo 0004
Person information
- affiliation: University of Electronic Science and Technology of China, The State Key Laboratory of Electronic Thin Films and Integrated Devices, Chengdu, China
Other persons with the same name
- Jian Luo — disambiguation page
- Jian Luo 0001 — Huawei Technologies Duesseldorf GmbH, European Research Center (ERC), Munich, Germany (and 2 more)
- Jian Luo 0002 — Central South University, School of Information Science and Engineering, Changsha, China (and 1 more)
- Jian Luo 0003 — Tsinghua University, School of Software, TNList, Beijing, China
- Jian Luo 0005 — East China Normal University, Institute of Biomedical Sciences, Shanghai, China (and 1 more)
- Jian Luo 0006 — Dongbei University of Finance and Economics, School of Management Science and Engineering, Dalian, China (and 1 more)
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2020 – today
2010 – 2019
- 2019
- [j4]Jian Luo, Jing Li, Shuangyi Wu, Ning Ning, Yang Liu:
A Bandwidth Mismatch Optimization Technique in Time-Interleaved Analog-to-Digital Converters. J. Circuits Syst. Comput. 28(6): 1950090:1-1950090:15 (2019) - [j3]Jing Li, Xin Ye, Jian Luo, Ning Ning, Qi Yu:
A Full-Band Timing Mismatch Calibration Technique in Time-Interleaved ADCs. J. Circuits Syst. Comput. 28(6): 1950092:1-1950092:14 (2019) - [c2]Jian Luo, Jing Li, Ning Ning, Kejun Wu, Zhen Liu, Yang Liu, Qi Yu:
A Low Voltage 10-Bit Non-Binary 2B/Cycle Time and Voltage Based SAR ADC. ISCAS 2019: 1-5 - 2018
- [j2]Jian Luo, Jing Li, Ning Ning, Yang Liu, Qi Yu:
The Effects of Comparator Dynamic Capacitor Mismatch in SAR ADC and Correction. IEEE Access 6: 7037-7043 (2018) - [j1]Jian Luo, Jing Li, Ning Ning, Yang Liu, Qi Yu:
A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1980-1988 (2018) - [c1]Jing Li, Jian Luo, Yongfeng Ding, Ning Ning:
A Supply Noise Compensation Circuit for Clock Buffers to Reduce Timing Jitter. APCCAS 2018: 86-89
Coauthor Index
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