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Raghu Sastry
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1990 – 1999
- 1998
- [j7]N. Ranganathan, Raghu Sastry, Raguveer Venkatesan:
SMAC: A VLSI Architecture for Scene Matching. Real Time Imaging 4(3): 171-180 (1998) - [j6]Raghu Sastry, N. Ranganathan:
A VLSI Architecture for Approximate Tree Matching. IEEE Trans. Computers 47(3): 346-352 (1998) - 1996
- [c7]Albert Mu, Jeff Larson, Raghu Sastry, Thomas Wicki, Winfried W. Wilcke:
A 9.6 GigaByte/s Throughput Plesiochronous Routing Chip. COMPCON 1996: 261-266 - 1995
- [j5]Raghu Sastry, N. Ranganathan:
PMAC: A Polygon Matching Chip. Int. J. Pattern Recognit. Artif. Intell. 9(2): 367-385 (1995) - [j4]Raghu Sastry, N. Ranganathan, Klinton Remedios:
CASM: A VLSI Chip for Approximate String Matching. IEEE Trans. Pattern Anal. Mach. Intell. 17(8): 824-830 (1995) - [j3]Raghu Sastry, N. Ranganathan, Ramesh C. Jain:
VLSI Architectures for High-Speed Range Estimation. IEEE Trans. Pattern Anal. Mach. Intell. 17(9): 894-899 (1995) - [c6]Raghu Sastry, N. Ranganathan:
A VLSI Architecture for Computer the Tree-to-Tree Distance. HPCA 1995: 330-339 - 1994
- [j2]N. Ranganathan, Raghu Sastry:
VLSI Architectures for Pattern Matching. Int. J. Pattern Recognit. Artif. Intell. 8(4): 815-843 (1994) - 1993
- [j1]Raghu Sastry, N. Ranganathan, Horst Bunke:
VLSI architectures for polygon recognition. IEEE Trans. Very Large Scale Integr. Syst. 1(4): 398-407 (1993) - [c5]N. Ranganathan, Raghu Sastry, Raguveer Venkatesan, Joseph W. Yoder, David C. Keezer:
SMAC: A Scene Matching Chip. ICCD 1993: 184-187 - [c4]Raghu Sastry, N. Ranganathan:
A Systolic Array for Approximate String Matching. ICCD 1993: 402-405 - [c3]Raghu Sastry, N. Ranganathan, Ramesh C. Jain:
VLSI Architectures for Depth Estimation Using Intensity Gradient Analysis. IPPS 1993: 700-704 - [c2]Raghu Sastry, N. Ranganathan, Horst Bunke:
Hardware Algorithms for Polygon Matching. VLSI Design 1993: 41-44 - 1992
- [c1]R. Venkatesan, Raghu Sastry, N. Ranganathan:
A VLSI architecture for hierarchical scene matching. ICPR (4) 1992: 214-217
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