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Chaojie He
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2020 – today
- 2024
- [j3]Shengzhe Yan, Jinshan Yue, Chaojie He, Zi Wang, Zhaori Cong, Yifan He, Mufeng Zhou, Wenyu Sun, Xueqing Li, Chunmeng Dou, Feng Zhang, Huazhong Yang, Yongpan Liu, Ming Liu:
A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture. IEEE J. Solid State Circuits 59(8): 2630-2643 (2024) - [j2]Chaojie He, Zi Wang, Feibin Xiang, Zhuoyu Dai, Yifan He, Jinshan Yue, Yongpan Liu:
LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design. IEEE Trans. Circuits Syst. II Express Briefs 71(2): 852-856 (2024) - 2023
- [j1]Zhuoyu Dai, Feibin Xiang, Chaojie He, Zi Wang, Woyu Zhang, Yi Li, Jinshan Yue, Dashan Shang:
A Scalable Small-Footprint Time-Space-Pipelined Architecture for Reservoir Computing. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 3069-3073 (2023) - [c2]Zi Wang, Jinshan Yue, Chaojie He, Zhuoyu Dai, Feibin Xiang, Zhaori Cong, Yifan He, Xiaoyu Feng, Yongpan Liu:
A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture. ISCAS 2023: 1-5 - [c1]Jinshan Yue, Chaojie He, Zi Wang, Zhaori Cong, Yifan He, Mufeng Zhou, Wenyu Sun, Xueqing Li, Chunmeng Dou, Feng Zhang, Huazhong Yang, Yongpan Liu, Ming Liu:
A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture. ISSCC 2023: 252-253
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last updated on 2024-08-23 18:26 CEST by the dblp team
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