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Deming Chen
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2020 – today
- 2024
- [j66]Anand Ramachandran
, Steven S. Lumetta, Deming Chen
:
PandoGen: Generating complete instances of future SARS-CoV-2 sequences using Deep Learning. PLoS Comput. Biol. 20(1) (2024) - [c196]Zehua Yuan, Junhao Pan, Xiaofan Zhang, Deming Chen:
HomeSGN: A Smarter Home with Novel Rule Mining Enabled by a Scorer-Generator GAN. ASPDAC 2024: 102-108 - [c195]Lily Jiaxin Wan, Yingbing Huang, Yuhong Li, Hanchen Ye, Jinghua Wang, Xiaofan Zhang, Deming Chen:
Invited Paper: Software/Hardware Co-design for LLM and Its Application for Design Verification. ASPDAC 2024: 435-441 - [c194]Hanchen Ye
, Hyegang Jun
, Deming Chen
:
HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis. ASPLOS (1) 2024: 215-230 - [c193]Hanchen Ye, David Z. Pan, Chris Leary, Deming Chen, Xiaoqing Xu:
Subgraph Extraction-Based Feedback-Guided Iterative Scheduling for HLS. DATE 2024: 1-6 - [c192]Deming Chen:
RAW 2024 Monday Keynote. IPDPS (Workshops) 2024: 82 - [i54]Tianle Cai, Yuhong Li, Zhengyang Geng, Hongwu Peng, Jason D. Lee, Deming Chen, Tri Dao:
Medusa: Simple LLM Inference Acceleration Framework with Multiple Decoding Heads. CoRR abs/2401.10774 (2024) - [i53]Hanchen Ye, David Z. Pan, Chris Leary, Deming Chen, Xiaoqing Xu:
Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS. CoRR abs/2401.12343 (2024) - [i52]Hongpeng Guo, Haotian Gu, Xiaoyang Wang, Bo Chen, Eun Kyung Lee, Tamar Eilam, Deming Chen, Klara Nahrstedt:
FedCore: Straggler-Free Federated Learning with Distributed Coresets. CoRR abs/2402.00219 (2024) - [i51]Sean Farhat, Deming Chen:
On the Surprising Efficacy of Distillation as an Alternative to Pre-Training Small Models. CoRR abs/2404.03263 (2024) - [i50]Daisuke Mashima, Yao Chen, Muhammad M. Roomi, Subhash Lakshminarayana, Deming Chen:
Cybersecurity for Modern Smart Grid against Emerging Threats. CoRR abs/2404.04466 (2024) - [i49]Yuhong Li, Yingbing Huang, Bowen Yang, Bharat Venkitesh, Acyr Locatelli, Hanchen Ye, Tianle Cai, Patrick Lewis, Deming Chen:
SnapKV: LLM Knows What You are Looking for Before Generation. CoRR abs/2404.14469 (2024) - [i48]Jingru Jia, Zehua Yuan, Junhao Pan, Paul McNamara, Deming Chen:
Decision-Making Behavior Evaluation Framework for LLMs under Uncertain Context. CoRR abs/2406.05972 (2024) - [i47]Yingbing Huang, Lily Jiaxin Wan, Hanchen Ye, Manvi Jha, Jinghua Wang, Yuhong Li, Xiaofan Zhang, Deming Chen:
New Solutions on LLM Acceleration, Optimization, and Application. CoRR abs/2406.10903 (2024) - 2023
- [j65]Daisuke Mashima, Yao Chen, Muhammad M. Roomi, Subhash Lakshminarayana, Deming Chen:
Cybersecurity for Modern Smart Grid Against Emerging Threats. Found. Trends Priv. Secur. 5(4): 189-285 (2023) - [j64]HyeGang Jun
, Hanchen Ye
, Hyunmin Jeong
, Deming Chen
:
AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis. ACM Trans. Reconfigurable Technol. Syst. 16(3): 46:1-46:30 (2023) - [c191]Deming Chen:
Lightning Talk: The Next Wave of High-level Synthesis. DAC 2023: 1-3 - [c190]Wei Ren, William Kozlowski, Sandhya Koteshwara, Mengmei Ye, Hubertus Franke, Deming Chen:
AccShield: a New Trusted Execution Environment with Machine-Learning Accelerators. DAC 2023: 1-6 - [c189]Meghna Mandava
, Deming Chen
:
Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization. FPGA 2023: 49 - [c188]Jinming Zhuang
, Jason Lau
, Hanchen Ye
, Zhuoping Yang
, Yubo Du
, Jack Lo
, Kristof Denolf
, Stephen Neuendorffer
, Alex K. Jones
, Jingtong Hu
, Deming Chen
, Jason Cong
, Peipei Zhou
:
CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture. FPGA 2023: 153-164 - [c187]Luyang Yu, Yizhen Lu, Meghna Mandava, Edward Richter, Vikram Sharma Mailthody, Seungwon Min, Wen-Mei W. Hwu, Deming Chen:
FSSD: FPGA-Based Emulator for SSDs. FPL 2023: 101-108 - [c186]Yizhen Lu, Luyang Yu, Deming Chen:
SSDe: FPGA-Based SSD Express Emulation Framework. ICCAD 2023: 1-9 - [c185]Yuhong Li, Jiajie Li, Cong Hao, Pan Li, Jinjun Xiong, Deming Chen:
Extensible and Efficient Proxy for Neural Architecture Search. ICCV 2023: 6176-6187 - [c184]Yuhong Li, Tianle Cai, Yi Zhang, Deming Chen, Debadeepta Dey:
What Makes Convolutional Models Great on Long Sequence Modeling? ICLR 2023 - [c183]Meghna Mandava
, Paul Reckamp
, Deming Chen
:
Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization. ISCA 2023: 60:1-60:13 - [c182]Hanchen Ye
, HyeGang Jun
, Jin Yang
, Deming Chen
:
High-level Synthesis for Domain Specific Computing. ISPD 2023: 211-219 - [c181]Benjamin Reidys
, Yuqi Xue
, Daixuan Li
, Bharat Sukhwani
, Wen-Mei Hwu
, Deming Chen
, Sameh W. Asaad
, Jian Huang
:
RackBlox: A Software-Defined Rack-Scale Storage System with Network-Storage Co-Design. SOSP 2023: 182-199 - [i46]Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Yubo Du, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex K. Jones
, Jingtong Hu, Deming Chen, Jason Cong, Peipei Zhou:
CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture. CoRR abs/2301.02359 (2023) - [i45]Benjamin Reidys, Yuqi Xue, Daixuan Li, Bharat Sukhwani, Wen-mei W. Hwu, Deming Chen, Sameh W. Asaad, Jian Huang:
RackBlox: A Software-Defined Rack-Scale Storage System with Network-Storage Co-Design. CoRR abs/2309.06513 (2023) - [i44]Hanchen Ye, HyeGang Jun, Deming Chen:
HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis. CoRR abs/2311.03379 (2023) - 2022
- [j63]Ashutosh Dhar
, Edward Richter
, Mang Yu, Wei Zuo, Xiaohao Wang, Nam Sung Kim
, Deming Chen
:
DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs. IEEE Trans. Computers 71(10): 2577-2591 (2022) - [j62]Jianwei Zheng
, Yu Liu, Xuejiao Liu, Luhong Liang, Deming Chen
, Kwang-Ting Cheng
:
ReAAP: A Reconfigurable and Algorithm-Oriented Array Processor With Compiler-Architecture Co-Design. IEEE Trans. Computers 71(12): 3088-3100 (2022) - [j61]Xiaofan Zhang
, Yuan Ma
, Jinjun Xiong
, Wen-Mei W. Hwu
, Volodymyr V. Kindratenko
, Deming Chen
:
Exploring HW/SW Co-Design for Video Analysis on CPU-FPGA Heterogeneous Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1606-1619 (2022) - [j60]Xiaofan Zhang
, Yuhong Li, Junhao Pan, Deming Chen
:
Algorithm/Accelerator Co-Design and Co-Search for Edge AI. IEEE Trans. Circuits Syst. II Express Briefs 69(7): 3064-3070 (2022) - [j59]Deming Chen:
Note from the TRETS EiC about the new Journal-first track in FPT'21. ACM Trans. Reconfigurable Technol. Syst. 15(1): 7e:1 (2022) - [j58]Xinyu Chen, Feng Cheng, Hongshi Tan, Yao Chen
, Bingsheng He, Weng-Fai Wong
, Deming Chen:
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS. ACM Trans. Reconfigurable Technol. Syst. 15(4): 44:1-44:31 (2022) - [c180]Xinheng Liu, Yao Chen
, Prakhar Ganesh, Junhao Pan, Jinjun Xiong
, Deming Chen:
HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation. ASP-DAC 2022: 140-146 - [c179]Hanchen Ye
, HyeGang Jun, Hyunmin Jeong, Stephen Neuendorffer, Deming Chen:
ScaleHLS: a scalable high-level synthesis framework with multi-level transformations and optimizations: invited. DAC 2022: 1355-1358 - [c178]Vibhakar Vemulapati, Deming Chen:
FSLAM: an Efficient and Accurate SLAM Accelerator on SoC FPGAs. FPT 2022: 1-9 - [c177]Hanchen Ye
, Cong Hao, Jianyi Cheng, Hyunmin Jeong, Jack Huang, Stephen Neuendorffer, Deming Chen:
ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation. HPCA 2022: 741-755 - [c176]Edward Richter, Deming Chen:
Qilin: Enabling Performance Analysis and Optimization of Shared-Virtual Memory Systems with FPGA Accelerators. ICCAD 2022: 23:1-23:9 - [c175]Deming Chen:
EDAML 2022 Invited Speaker 2: AI Algorithm and Accelerator Co-design for Computing on the Edge. IPDPS Workshops 2022: 1183 - [c174]Junhao Pan, Zehua Yuan, Xiaofan Zhang, Deming Chen:
YouHome System and Dataset: Making Your Home Know You Better. iSES 2022: 414-420 - [c173]Hongpeng Guo
, Haotian Gu, Zhe Yang, Xiaoyang Wang, Eun Kyung Lee, Nandhini Chandramoorthy, Tamar Eilam, Deming Chen, Klara Nahrstedt:
BoFL: bayesian optimized local training pace control for energy efficient federated learning. Middleware 2022: 188-201 - [c172]Prakhar Ganesh, Yao Chen, Yin Yang, Deming Chen, Marianne Winslett:
YOLO-ReT: Towards High Accuracy Real-time Object Detection on Edge GPUs. WACV 2022: 1311-1321 - [p2]S. T. Choden Konigsmark, Wei Ren, Martin D. F. Wong, Deming Chen:
High-Level Synthesis for Minimizing Power Side-Channel Information Leakage. Behavioral Synthesis for Hardware Security 2022: 291-317 - [i43]Xiaofan Zhang, Zongwei Zhou, Deming Chen, Yu Emma Wang:
AutoDistill: an End-to-End Framework to Explore and Distill Hardware-Efficient Language Models. CoRR abs/2201.08539 (2022) - [i42]Philip C. Harris, Erik Katsavounidis, William Patrick McCormack, Dylan S. Rankin
, Yongbin Feng, Abhijith Gandrakota, Christian Herwig, Burt Holzman, Kevin Pedro, Nhan Tran, Tingjun Yang, Jennifer Ngadiuba, Michael Coughlin, Scott Hauck, Shih-Chieh Hsu, Elham E Khoda, Deming Chen, Mark S. Neubauer, Javier M. Duarte, Georgia Karagiorgi, Mia Liu:
Physics Community Needs, Tools, and Resources for Machine Learning. CoRR abs/2203.16255 (2022) - [i41]Xiaofan Zhang, Yao Chen, Cong Hao, Sitao Huang, Yuhong Li, Deming Chen:
Efficient Machine Learning, Compilers, and Optimizations for Embedded Systems. CoRR abs/2206.03326 (2022) - [i40]Mang Yu, Sitao Huang, Deming Chen:
Chimera: A Hybrid Machine Learning Driven Multi-Objective Design Space Exploration Tool for FPGA High-Level Synthesis. CoRR abs/2207.07917 (2022) - [i39]Yao Chen, Junhao Pan, Xinheng Liu, Jinjun Xiong
, Deming Chen:
HiKonv: Maximizing the Throughput of Quantized Convolution With Novel Bit-wise Management and Computation. CoRR abs/2208.00763 (2022) - [i38]Yuhong Li, Tianle Cai, Yi Zhang, Deming Chen, Debadeepta Dey:
What Makes Convolutional Models Great on Long Sequence Modeling? CoRR abs/2210.09298 (2022) - [i37]Yuhong Li, Jiajie Li, Cong Han, Pan Li, Jinjun Xiong
, Deming Chen:
Extensible Proxy for Efficient NAS. CoRR abs/2210.09459 (2022) - 2021
- [j57]Anand Ramachandran, Steven S. Lumetta, Eric W. Klee, Deming Chen
:
HELLO: improved neural network architectures and methodologies for small variant calling. BMC Bioinform. 22(1): 404 (2021) - [j56]Luca Benini, Deming Chen
, Jinjun Xiong
, Zhiru Zhang
:
Guest Editors' Introduction: Machine Intelligence at the Edge. IEEE Des. Test 38(4): 5-6 (2021) - [j55]Cong Hao, Jordan Dotzel
, Jinjun Xiong
, Luca Benini
, Zhiru Zhang
, Deming Chen
:
Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Codesign. IEEE Des. Test 38(4): 7-26 (2021) - [j54]Seungwon Min, Kun Wu
, Sitao Huang, Mert Hidayetoglu
, Jinjun Xiong
, Eiman Ebrahimi, Deming Chen, Wen-mei W. Hwu:
Large Graph Convolutional Network Training with GPU-Oriented Data Communication Architecture. Proc. VLDB Endow. 14(11): 2087-2100 (2021) - [j53]Prakhar Ganesh, Yao Chen, Xin Lou, Mohammad Ali Khan, Yin Yang, Hassan Sajjad
, Preslav Nakov, Deming Chen, Marianne Winslett:
Compressing Large-Scale Transformer-Based Models: A Case Study on BERT. Trans. Assoc. Comput. Linguistics 9: 1061-1080 (2021) - [j52]Jianwei Zheng
, Chao Lu
, Cong Hao
, Deming Chen
, Donghui Guo
:
Improving the Generalization Ability of Deep Neural Networks for Cross-Domain Visual Recognition. IEEE Trans. Cogn. Dev. Syst. 13(3): 607-620 (2021) - [j51]Cheng Gong
, Yao Chen
, Ye Lu
, Tao Li
, Cong Hao, Deming Chen
:
VecQ: Minimal Loss DNN Model Compression With Vectorized Weight Quantization. IEEE Trans. Computers 70(5): 696-710 (2021) - [j50]Sitao Huang
, Kun Wu
, Hyunmin Jeong, Chengyue Wang, Deming Chen
, Wen-Mei Hwu
:
PyLog: An Algorithm-Centric Python-Based FPGA Programming and Synthesis Flow. IEEE Trans. Computers 70(12): 2015-2028 (2021) - [j49]Qin Li, Xiaofan Zhang
, Jinjun Xiong
, Wen-Mei Hwu, Deming Chen
:
Efficient Methods for Mapping Neural Machine Translator on FPGAs. IEEE Trans. Parallel Distributed Syst. 32(7): 1866-1877 (2021) - [j48]Prakhar Ganesh
, Xin Lou
, Yao Chen
, Rui Tan
, David K. Y. Yau, Deming Chen
, Marianne Winslett
:
Learning-Based Simultaneous Detection and Characterization of Time Delay Attack in Cyber-Physical Systems. IEEE Trans. Smart Grid 12(4): 3581-3593 (2021) - [c171]Cong Hao, Deming Chen:
Software/Hardware Co-design for Multi-modal Multi-task Learning in Autonomous Systems. AICAS 2021: 1-5 - [c170]Ashutosh Dhar, Paul Reckamp, Jinjun Xiong
, Wen-Mei Hwu, Deming Chen:
Graviton: A Reconfigurable Memory-Compute Fabric for Data Intensive Applications. ARC 2021: 254-264 - [c169]Hyunmin Jeong, Deming Chen:
TwinDNN: A Tale of Two Deep Neural Networks. ASAP 2021: 133-140 - [c168]Xinheng Liu, Yao Chen
, Cong Hao, Ashutosh Dhar, Deming Chen:
WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs. ASAP 2021: 258-265 - [c167]Junhao Pan, Deming Chen:
Accelerate Non-unit Stride Convolutions with Winograd Algorithms. ASP-DAC 2021: 358-364 - [c166]Sitao Huang, Aayush Ankit, Plínio Silveira, Rodrigo Antunes, Sai Rahul Chalamalasetti, Izzat El Hajj, Dong Eun Kim
, Glaucimar Aguiar, Pedro Bruel, Sergey Serebryakov
, Cong Xu, Can Li, Paolo Faraboschi, John Paul Strachan, Deming Chen, Kaushik Roy, Wen-Mei W. Hwu, Dejan S. Milojicic:
Mixed Precision Quantization for ReRAM-based DNN Inference Accelerators. ASP-DAC 2021: 372-377 - [c165]Xiaofan Zhang, Dawei Wang, Pierce Chuang, Shugao Ma, Deming Chen, Yuecheng Li:
F-CAD: A Framework to Explore Hardware Accelerators for Codec Avatar Decoding. DAC 2021: 763-768 - [c164]Xinyu Chen, Hongshi Tan, Yao Chen
, Bingsheng He, Weng-Fai Wong
, Deming Chen:
Skew-Oblivious Data Routing for Data Intensive Applications on FPGAs with HLS. DAC 2021: 937-942 - [c163]Chengyue Wang, Sitao Huang, Wen-Mei Hwu, Deming Chen:
Extending HLS with High-Level Descriptive Language for Configurable Algorithm-Level Spatial Structure Design. FCCM 2021: 261 - [c162]Hyunmin Jeong, Deming Chen:
TwinDNN: A Tale of Two Deep Neural Networks. FCCM 2021: 276 - [c161]Saranyu Chattopadhyay
, Florian Lonsing, Luca Piccolboni, Deepraj Soni, Peng Wei, Xiaofan Zhang, Yuan Zhou, Luca P. Carloni, Deming Chen, Jason Cong, Ramesh Karri, Zhiru Zhang, Caroline Trippel, Clark W. Barrett, Subhasish Mitra:
Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition. FMCAD 2021: 42-52 - [c160]Xinyu Chen, Hongshi Tan, Yao Chen
, Bingsheng He, Weng-Fai Wong
, Deming Chen:
ThunderGP: HLS-based Graph Processing Framework on FPGAs. FPGA 2021: 69-80 - [c159]Yichi Zhang
, Junhao Pan, Xinheng Liu, Hongzheng Chen
, Deming Chen, Zhiru Zhang
:
FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations. FPGA 2021: 171-182 - [c158]Sitao Huang, Kun Wu, Hyunmin Jeong, Chengyue Wang, Deming Chen, Wen-Mei Hwu:
PyLog: An Algorithm-Centric Python-Based FPGA Programming and Synthesis Flow. FPGA 2021: 227-228 - [c157]Enliang Li, Subho S. Banerjee
, Sitao Huang, Ravishankar K. Iyer, Deming Chen:
Improved GPU Implementations of the Pair-HMM Forward Algorithm for DNA Sequence Alignment. ICCD 2021: 299-306 - [c156]Mang Yu, Sitao Huang, Deming Chen:
Chimera: A Hybrid Machine Learning-Driven Multi-Objective Design Space Exploration Tool for FPGA High-Level Synthesis. IDEAL 2021: 524-536 - [c155]Wei Ren, Junhao Pan, Deming Chen:
AccGuard: Secure and Trusted Computation on Remote FPGA Accelerators. iSES 2021: 378-383 - [c154]Yuhong Li, Cong Hao, Pan Li, Jinjun Xiong, Deming Chen:
Generic Neural Architecture Search via Regression. NeurIPS 2021: 20476-20490 - [c153]Sitao Huang, Kun Wu, Sai Rahul Chalamalasetti, Izzat El Hajj, Cong Xu, Paolo Faraboschi, Deming Chen:
A Python-based High-Level Programming Flow for CPU-FPGA Heterogeneous Systems : (Invited Paper). PEHC@SC 2021: 20-26 - [i36]Seungwon Min, Kun Wu, Sitao Huang, Mert Hidayetoglu, Jinjun Xiong, Eiman Ebrahimi, Deming Chen, Wen-Mei W. Hwu:
PyTorch-Direct: Enabling GPU Centric Data Access for Very Large Graph Neural Network Training with Irregular Accesses. CoRR abs/2101.07956 (2021) - [i35]Seungwon Min, Kun Wu, Sitao Huang, Mert Hidayetoglu, Jinjun Xiong, Eiman Ebrahimi, Deming Chen, Wen-Mei W. Hwu:
Large Graph Convolutional Network Training with GPU-Oriented Data Communication Architecture. CoRR abs/2103.03330 (2021) - [i34]Xiaofan Zhang, Dawei Wang, Pierce Chuang, Shugao Ma, Deming Chen, Yuecheng Li:
F-CAD: A Framework to Explore Hardware Accelerators for Codec Avatar Decoding. CoRR abs/2103.04958 (2021) - [i33]Cong Hao, Jordan Dotzel, Jinjun Xiong, Luca Benini, Zhiru Zhang, Deming Chen:
Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Co-design. CoRR abs/2103.15750 (2021) - [i32]Xiaofan Zhang, Hanchen Ye, Deming Chen:
Being-ahead: Benchmarking and Exploring Accelerators for Hardware-Efficient AI Deployment. CoRR abs/2104.02251 (2021) - [i31]Cong Hao, Deming Chen:
Software/Hardware Co-design for Multi-modal Multi-task Learning in Autonomous Systems. CoRR abs/2104.04000 (2021) - [i30]Xinyu Chen, Hongshi Tan, Yao Chen, Bingsheng He, Weng-Fai Wong, Deming Chen:
Skew-Oblivious Data Routing for Data-Intensive Applications on FPGAs with HLS. CoRR abs/2105.04151 (2021) - [i29]Xinheng Liu, Yao Chen, Cong Hao, Ashutosh Dhar, Deming Chen:
WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs. CoRR abs/2107.04244 (2021) - [i28]Hanchen Ye, Cong Hao, Jianyi Cheng, Hyunmin Jeong, Jack Huang, Stephen Neuendorffer, Deming Chen:
ScaleHLS: Scalable High-Level Synthesis through MLIR. CoRR abs/2107.11673 (2021) - [i27]Yuhong Li, Cong Hao, Pan Li, Jinjun Xiong, Deming Chen:
Generic Neural Architecture Search via Regression. CoRR abs/2108.01899 (2021) - [i26]Saranyu Chattopadhyay, Florian Lonsing, Luca Piccolboni, Deepraj Soni, Peng Wei, Xiaofan Zhang, Yuan Zhou, Luca P. Carloni, Deming Chen, Jason Cong, Ramesh Karri, Zhiru Zhang, Caroline Trippel, Clark W. Barrett, Subhasish Mitra:
Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition. CoRR abs/2108.06081 (2021) - [i25]Prakhar Ganesh, Yao Chen, Yin Yang, Deming Chen, Marianne Winslett:
YOLO-ReT: Towards High Accuracy Real-time Object Detection on Edge GPUs. CoRR abs/2110.13713 (2021) - [i24]Qian Jiang, Xiaofan Zhang, Deming Chen, Minh N. Do, Raymond A. Yeh:
EH-DNAS: End-to-End Hardware-aware Differentiable Neural Architecture Search. CoRR abs/2111.12299 (2021) - [i23]Xinheng Liu, Yao Chen, Prakhar Ganesh, Junhao Pan, Jinjun Xiong, Deming Chen:
HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation. CoRR abs/2112.13972 (2021) - 2020
- [c152]Dae Hee Kim, Rakesh Nagi
, Deming Chen:
Thanos: High-Performance CPU-GPU Based Balanced Graph Partitioning Using Cross-Decomposition. ASP-DAC 2020: 91-96 - [c151]Xinyu Chen, Yao Chen, Ronak Bajaj, Jiong He, Bingsheng He, Weng-Fai Wong, Deming Chen:
Is FPGA Useful for Hash Joins? CIDR 2020 - [c150]Yuhong Li, Cong Hao, Xiaofan Zhang, Xinheng Liu, Yao Chen
, Jinjun Xiong
, Wen-mei W. Hwu, Deming Chen:
EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions. DAC 2020: 1-6 - [c149]Eshan Singh, Florian Lonsing, Saranyu Chattopadhyay
, Maxwell Strange, Peng Wei, Xiaofan Zhang, Yuan Zhou, Deming Chen, Jason Cong, Priyanka Raina, Zhiru Zhang
, Clark W. Barrett, Subhasish Mitra
:
A-QED Verification of Hardware Accelerators. DAC 2020: 1-6 - [c148]Hanchen Ye
, Xiaofan Zhang, Zhize Huang, Gengsheng Chen, Deming Chen:
HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation. DAC 2020: 1-6 - [c147]Pengfei Xu, Xiaofan Zhang, Cong Hao, Yang Zhao
, Yongan Zhang, Yue Wang, Chaojian Li, Zetong Guan, Deming Chen, Yingyan Lin:
AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs. FPGA 2020: 40-50 - [c146]Cong Hao, Yao Chen
, Xiaofan Zhang, Yuhong Li, Jinjun Xiong
, Wen-Mei Hwu, Deming Chen:
Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devices. ACM Great Lakes Symposium on VLSI 2020: 283-290 - [c145]Xiaofan Zhang, Hanchen Ye
, Junsong Wang, Yonghua Lin, Jinjun Xiong
, Wen-Mei Hwu, Deming Chen:
DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator. ICCAD 2020: 61:1-61:9 - [c144]Yao Chen
, Xin Long, Jiong He, Yuhang Chen, Hongshi Tan, Zhenxiang Zhang, Marianne Winslett, Deming Chen:
HaoCL: Harnessing Large-scale Heterogeneous Processors Made Easy. ICDCS 2020: 1231-1234 - [c143]Ashutosh Dhar, Xiaohao Wang, Hubertus Franke, Jinjun Xiong
, Jian Huang, Wen-Mei W. Hwu, Nam Sung Kim, Deming Chen:
FReaC Cache: Folded-logic Reconfigurable Computing in the Last Level Cache. MICRO 2020: 102-117 - [c142]Xiaofan Zhang, Haoming Lu, Cong Hao, Jiachen Li, Bowen Cheng, Yuhong Li, Kyle Rupnow, Jinjun Xiong, Thomas S. Huang, Honghui Shi, Wen-Mei Hwu, Deming Chen:
SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on Embedded Systems. MLSys 2020 - [c141]Ashutosh Dhar, Mang Yu, Wei Zuo, Xiaohao Wang, Nam Sung Kim, Deming Chen:
Leveraging Dynamic Partial Reconfiguration with Scalable ILP Based Task Scheduling. VLSID 2020: 201-206 - [i22]Pengfei Xu, Xiaofan Zhang, Cong Hao, Yang Zhao, Yongan Zhang, Yue Wang, Chaojian Li, Zetong Guan, Deming Chen, Yingyan Lin:
AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs. CoRR abs/2001.03535 (2020) - [i21]Prakhar Ganesh
, Yao Chen
, Xin Lou, Mohammad Ali Khan, Yin Yang, Deming Chen, Marianne Winslett, Hassan Sajjad, Preslav Nakov:
Compressing Large-Scale Transformer-Based Models: A Case Study on BERT. CoRR abs/2002.11985 (2020) - [i20]Hanchen Ye, Xiaofan Zhang, Zhize Huang, Gengsheng Chen, Deming Chen:
HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation. CoRR abs/2004.03804 (2020) - [i19]Yuhong Li, Cong Hao, Xiaofan Zhang, Xinheng Liu, Yao Chen, Jinjun Xiong, Wen-Mei W. Hwu, Deming Chen:
EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions. CoRR abs/2005.02563 (2020) - [i18]Yao Chen, Xin Long, Jiong He, Yuhang Chen, Hongshi Tan, Zhenxiang Zhang, Marianne Winslett, Deming Chen:
HaoCL: Harnessing Large-scale Heterogeneous Processors Made Easy. CoRR abs/2005.08466 (2020) - [i17]Cheng Gong, Yao Chen, Ye Lu, Tao Li, Cong Hao, Deming Chen:
VecQ: Minimal Loss DNN Model Compression With Vectorized Weight Quantization. CoRR abs/2005.08501 (2020) - [i16]Xiaofan Zhang, Hanchen Ye, Junsong Wang, Yonghua Lin, Jinjun Xiong, Wen-Mei W. Hwu, Deming Chen:
DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator. CoRR abs/2008.12745 (2020) - [i15]Cong Hao, Yao Chen, Xiaofan Zhang, Yuhong Li, Jinjun Xiong, Wen-Mei Hwu, Deming Chen:
Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devices. CoRR abs/2010.07185 (2020) - [i14]Yichi Zhang, Junhao Pan, Xinheng Liu, Hongzheng Chen, Deming Chen, Zhiru Zhang:
FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations. CoRR abs/2012.12206 (2020)
2010 – 2019
- 2019
- [j47]Subho S. Banerjee
, Mohamed El-Hadedy, Jong Bin Lim, Zbigniew T. Kalbarczyk, Deming Chen, Steven S. Lumetta, Ravishankar K. Iyer
:
ASAP: Accelerated Short-Read Alignment on Programmable Hardware. IEEE Trans. Computers 68(3): 331-346 (2019) - [j46]Keith A. Campbell
, Chen-Hsuan Lin
, Deming Chen:
Cost-Effective Error Detection Through Mersenne Modulo Shadow Datapaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1056-1069 (2019) - [j45]Keith A. Campbell
, David Lin, Leon He
, Liwei Yang, Swathi T. Gurumani, Kyle Rupnow
, Subhasish Mitra
, Deming Chen:
Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1345-1358 (2019) - [j44]Jianwei Zheng, Chao Lu, Jiefeng Guo, Deming Chen, Donghui Guo:
A Hardware-Efficient Block Matching Algorithm and Its Hardware Design for Variable Block Size Motion Estimation in Ultra-High-Definition Video Encoding. ACM Trans. Design Autom. Electr. Syst. 24(2): 15:1-15:21 (2019) - [j43]Deming Chen:
Editorial: A Message from the New Editor-in-Chief. ACM Trans. Reconfigurable Technol. Syst. 12(2) (2019) - [c140]Anand Ramachandran, Steven S. Lumetta, Eric W. Klee, Deming Chen:
A recurrent Markov state-space generative model for sequences. AISTATS 2019: 3070-3079 - [c139]Qin Li, Xiaofan Zhang, Jinjun Xiong
, Wen-Mei Hwu, Deming Chen:
Implementing neural machine translation with bi-directional GRU and attention mechanism on FPGAs using HLS. ASP-DAC 2019: 693-698 - [c138]Eric Cheng, Daniel Mueller-Gritschneder
, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Deming Chen, Hyungmin Cho, Yanjing Li, Uzair Sharif, Kevin Skadron
, Mircea Stan
, Ulf Schlichtmann
, Subhasish Mitra:
Cross-Layer Resilience: Challenges, Insights, and the Road Ahead. DAC 2019: 198 - [c137]Cong Hao, Xiaofan Zhang, Yuhong Li, Sitao Huang, Jinjun Xiong
, Kyle Rupnow, Wen-Mei Hwu, Deming Chen:
FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge. DAC 2019: 206 - [c136]Yao Chen
, Jiong He, Xiaofan Zhang, Cong Hao, Deming Chen:
Cloud-DNN: An Open Framework for Mapping DNN Models to Cloud FPGAs. FPGA 2019: 73-82 - [c135]Deming Chen:
FPGAs in Supercomputers: Opportunity or Folly? FPGA 2019: 201 - [c134]Xinyu Chen, Ronak Bajaj, Yao Chen
, Jiong He, Bingsheng He
, Weng-Fai Wong
, Deming Chen:
On-The-Fly Parallel Data Shuffling for Graph Processing on OpenCL-Based FPGAs. FPL 2019: 67-73 - [c133]Seungwon Min, Sitao Huang, Mohamed El-Hadedy, Jinjun Xiong
, Deming Chen, Wen-Mei Hwu:
Analysis and Optimization of I/O Cache Coherency Strategies for SoC-FPGA Device. FPL 2019: 301-306 - [c132]Sitao Huang, Carl Pearson, Rakesh Nagi
, Jinjun Xiong
, Deming Chen, Wen-Mei W. Hwu:
Accelerating Sparse Deep Neural Networks on FPGAs. HPEC 2019: 1-7 - [c131]Di He, Xuesong Yang
, Boon Pang Lim, Yi Liang, Mark Hasegawa-Johnson, Deming Chen:
When CTC Training Meets Acoustic Landmarks. ICASSP 2019: 5996-6000 - [c130]Cong Hao, Yao Chen
, Xinheng Liu, Atif Sarwari, Daryl Sew, Ashutosh Dhar, Bryan Wu, Dongdong Fu, Jinjun Xiong
, Wen-Mei Hwu, Junli Gu, Deming Chen:
NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving. ICCAD 2019: 1-8 - [c129]Cheng Gong
, Tao Li, Ye Lu, Cong Hao, Xiaofan Zhang, Deming Chen, Yao Chen
:
µL2Q: An Ultra-Low Loss Quantization Method for DNN Compression. IJCNN 2019: 1-8 - [c128]Youjie Li, Iou-Jen Liu, Yifan Yuan, Deming Chen, Alexander G. Schwing, Jian Huang:
Accelerating distributed reinforcement learning with in-switch computing. ISCA 2019: 279-291 - [c127]Yao Chen
, Kai Zhang, Cheng Gong
, Cong Hao, Xiaofan Zhang, Tao Li, Deming Chen:
T-DLA: An Open-source Deep Learning Accelerator for Ternarized DNN Models on Embedded FPGA. ISVLSI 2019: 13-18 - [c126]Ashutosh Dhar, Sitao Huang, Jinjun Xiong
, Damir A. Jamsek, Bruno Mesnet, Jian Huang, Nam Sung Kim, Wen-Mei W. Hwu, Deming Chen:
Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing Workloads. ISVLSI 2019: 68-75 - [c125]Jong Bin Lim, Deming Chen:
Automated Communication and Floorplan-Aware Hardware/Software Co-Design for SoC. ISVLSI 2019: 128-133 - [c124]Cong Hao, Junli Gu, Deming Chen, Atif Sarwari, Zhijie Jin, Husam Abu-Haimed, Daryl Sew, Yuhong Li, Xinheng Liu, Bryan Wu, Dongdong Fu:
A Hybrid GPU + FPGA System Design for Autonomous Driving Cars. SiPS 2019: 121-126 - [c123]Sitao Huang, Li-Wen Chang, Izzat El Hajj, Simon Garcia De Gonzalo, Juan Gómez-Luna, Sai Rahul Chalamalasetti, Mohamed El-Hadedy, Dejan S. Milojicic
, Onur Mutlu, Deming Chen, Wen-Mei W. Hwu:
Analysis and Modeling of Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures. ICPE 2019: 79-90 - [i13]Cong Hao, Xiaofan Zhang, Yuhong Li, Sitao Huang, Jinjun Xiong, Kyle Rupnow, Wen-Mei Hwu, Deming Chen:
FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge. CoRR abs/1904.04421 (2019) - [i12]Xiaofan Zhang, Cong Hao, Yuhong Li, Yao Chen
, Jinjun Xiong, Wen-Mei W. Hwu, Deming Chen:
A Bi-Directional Co-Design Approach to Enable Deep Learning on IoT Devices. CoRR abs/1905.08369 (2019) - [i11]Xiaofan Zhang, Cong Hao, Haoming Lu, Jiachen Li, Yuhong Li, Yuchen Fan, Kyle Rupnow, Jinjun Xiong, Thomas S. Huang, Honghui Shi, Wen-Mei Hwu, Deming Chen:
SkyNet: A Champion Model for DAC-SDC on Low Power Object Detection. CoRR abs/1906.10327 (2019) - [i10]Seungwon Min, Sitao Huang, Mohamed El-Hadedy, Jinjun Xiong, Deming Chen, Wen-Mei Hwu:
Analysis and Optimization of I/O Cache Coherency Strategies for SoC-FPGA Device. CoRR abs/1908.01261 (2019) - [i9]Xiaofan Zhang, Haoming Lu, Cong Hao, Jiachen Li, Bowen Cheng, Yuhong Li, Kyle Rupnow, Jinjun Xiong, Thomas S. Huang, Honghui Shi, Wen-mei W. Hwu, Deming Chen:
SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on Embedded Systems. CoRR abs/1909.09709 (2019) - [i8]Cong Hao, Yao Chen, Xinheng Liu, Atif Sarwari, Daryl Sew, Ashutosh Dhar, Bryan Wu, Dongdong Fu, Jinjun Xiong, Wen-Mei Hwu, Junli Gu, Deming Chen:
NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving. CoRR abs/1911.07446 (2019) - 2018
- [j42]Morteza Gholipour
, Ying-Yu Chen, Deming Chen:
Compact Modeling to Device- and Circuit-Level Evaluation of Flexible TMD Field-Effect Transistors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 820-831 (2018) - [j41]Chen-Hsuan Lin, Lu Wan, Deming Chen:
C-Mine: Data Mining of Logic Common Cases for Improved Timing Error Resilience with Energy Efficiency. ACM Trans. Design Autom. Electr. Syst. 23(2): 20:1-20:23 (2018) - [j40]Deming Chen, Andrew Putnam, Steven J. E. Wilton:
Introduction to the Special Section on Deep Learning in FPGAs. ACM Trans. Reconfigurable Technol. Syst. 11(3): 14:1-14:3 (2018) - [c122]Huiren Li, Anand Ramachandran, Deming Chen:
GPU Acceleration of Advanced k-mer Counting for Computational Genomics. ASAP 2018: 1-4 - [c121]Anand Ramachandran, Huiren Li, Eric W. Klee, Steven S. Lumetta, Deming Chen:
Deep Learning for Better Variant Calling for Cancer Diagnosis and Treatment. ASP-DAC 2018: 16-21 - [c120]Keith A. Campbell, Chen-Hsuan Lin, Deming Chen:
Low-cost hardware architectures for mersenne modulo functional units. ASP-DAC 2018: 599-604 - [c119]Yuhong Li, Xiaofan Zhang, Deming Chen:
CSRNet: Dilated Convolutional Neural Networks for Understanding the Highly Congested Scenes. CVPR 2018: 1091-1100 - [c118]Xinheng Liu, Dae Hee Kim, Chang Wu, Deming Chen:
Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices. SLIP@DAC 2018: 1:1-1:8 - [c117]Matej Kristan, Ales Leonardis, Jiri Matas
, Michael Felsberg
, Roman P. Pflugfelder, Luka Cehovin Zajc, Tomás Vojír, Goutam Bhat, Alan Lukezic, Abdelrahman Eldesokey, Gustavo Fernández, Álvaro García-Martín, Álvaro Iglesias-Arias, A. Aydin Alatan, Abel González-García, Alfredo Petrosino, Alireza Memarmoghadam
, Andrea Vedaldi, Andrej Muhic, Anfeng He, Arnold W. M. Smeulders, Asanka G. Perera
, Bo Li, Boyu Chen, Changick Kim, Changsheng Xu, Changzhen Xiong, Cheng Tian, Chong Luo, Chong Sun, Cong Hao, Daijin Kim, Deepak Mishra, Deming Chen, Dong Wang, Dongyoon Wee, Efstratios Gavves, Erhan Gundogdu, Erik Velasco-Salido
, Fahad Shahbaz Khan, Fan Yang, Fei Zhao, Feng Li, Francesco Battistone, George De Ath
, Gorthi R. K. Sai Subrahmanyam, Guilherme Sousa Bastos
, Haibin Ling, Hamed Kiani Galoogahi, Hankyeol Lee, Haojie Li, Haojie Zhao, Heng Fan, Honggang Zhang, Horst Possegger, Houqiang Li, Huchuan Lu, Hui Zhi, Huiyun Li, Hyemin Lee, Hyung Jin Chang, Isabela Drummond, Jack Valmadre, Jaime Spencer Martin
, Javaan Singh Chahl
, Jin Young Choi, Jing Li, Jinqiao Wang, Jinqing Qi, Jinyoung Sung, Joakim Johnander, João F. Henriques, Jongwon Choi, Joost van de Weijer
, Jorge Rodríguez Herranz, José M. Martínez, Josef Kittler, Junfei Zhuang, Junyu Gao, Klemen Grm, Lichao Zhang, Lijun Wang, Lingxiao Yang, Litu Rout
, Liu Si, Luca Bertinetto, Lutao Chu, Manqiang Che, Mario Edoardo Maresca, Martin Danelljan, Ming-Hsuan Yang, Mohamed H. Abdelpakey, Mohamed S. Shehata
, Myunggu Kang, Namhoon Lee, Ning Wang, Ondrej Miksik, Payman Moallem
, Pablo Vicente-Moñivar, Pedro Senna, Peixia Li, Philip H. S. Torr, Priya Mariam Raju, Ruihe Qian, Qiang Wang, Qin Zhou, Qing Guo
, Rafael Martin Nieto, Rama Krishna Sai Subrahmanyam Gorthi, Ran Tao, Richard Bowden
, Richard M. Everson, Runling Wang, Sangdoo Yun, Seokeon Choi, Sergio Vivas, Shuai Bai, Shuangping Huang, Sihang Wu, Simon Hadfield
, Siwen Wang, Stuart Golodetz, Ming Tang, Tianyang Xu
, Tianzhu Zhang, Tobias Fischer
, Vincenzo Santopietro, Vitomir Struc, Wei Wang, Wangmeng Zuo, Wei Feng, Wei Wu, Wei Zou, Weiming Hu, Wengang Zhou, Wenjun Zeng, Xiaofan Zhang, Xiaohe Wu, Xiao-Jun Wu, Xinmei Tian, Yan Li, Yan Lu, Yee Wei Law
, Yi Wu, Yiannis Demiris
, Yicai Yang, Yifan Jiao, Yuhong Li, Yunhua Zhang, Yuxuan Sun, Zheng Zhang, Zheng Zhu, Zhen-Hua Feng, Zhihui Wang, Zhiqun He:
The Sixth Visual Object Tracking VOT2018 Challenge Results. ECCV Workshops (1) 2018: 3-53 - [c116]Xiaofan Zhang, Junsong Wang, Chao Zhu, Yonghua Lin, Jinjun Xiong
, Wen-Mei W. Hwu, Deming Chen:
AccDNN: An IP-Based DNN Generator for FPGAs. FCCM 2018: 210 - [c115]Junsong Wang, Qiuwen Lou, Xiaofan Zhang, Chao Zhu, Yonghua Lin, Deming Chen:
Design Flow of Accelerating Hybrid Extremely Low Bit-Width Neural Network in Embedded FPGA. FPL 2018: 163-169 - [c114]Chuanhao Zhuge, Xinheng Liu, Xiaofan Zhang, Sudeep Gummadi, Jinjun Xiong
, Deming Chen:
Face Recognition with Hybrid Efficient Convolution Algorithms on FPGAs. ACM Great Lakes Symposium on VLSI 2018: 123-128 - [c113]Sitao Huang, Mohamed El-Hadedy, Cong Hao, Qin Li, Vikram S. Mailthody
, Ketan Date, Jinjun Xiong
, Deming Chen, Rakesh Nagi
, Wen-Mei Hwu:
Triangle Counting and Truss Decomposition using FPGA. HPEC 2018: 1-7 - [c112]Xiaofan Zhang, Junsong Wang, Chao Zhu, Yonghua Lin, Jinjun Xiong
, Wen-Mei W. Hwu, Deming Chen:
DNNBuilder: an automated tool for building high-performance DNN hardware accelerators for FPGAs. ICCAD 2018: 56 - [c111]Di He, Boon Pang Lim, Xuesong Yang
, Mark Hasegawa-Johnson, Deming Chen:
Improved ASR for Under-resourced Languages through Multi-task Learning with Acoustic Landmarks. INTERSPEECH 2018: 2618-2622 - [c110]Mohammad Alian
, Seungwon Min, Hadi Asgharimoghaddam, Ashutosh Dhar, Dong Kai Wang
, Thomas Roewer, Adam J. McPadden, Oliver O'Halloran, Deming Chen, Jinjun Xiong
, Daehoon Kim, Wen-Mei W. Hwu, Nam Sung Kim:
Application-Transparent Near-Memory Processing Architecture with Memory Channel Network. MICRO 2018: 802-814 - [e5]Deming Chen, Houman Homayoun, Baris Taskin:
Proceedings of the 2018 on Great Lakes Symposium on VLSI, GLSVLSI 2018, Chicago, IL, USA, May 23-25, 2018. ACM 2018 [contents] - [i7]Yuhong Li, Xiaofan Zhang, Deming Chen:
CSRNet: Dilated Convolutional Neural Networks for Understanding the Highly Congested Scenes. CoRR abs/1802.10062 (2018) - [i6]Subho S. Banerjee
, Mohamed El-Hadedy, Jong Bin Lim, Zbigniew T. Kalbarczyk, Deming Chen, Steven S. Lumetta, Ravishankar K. Iyer:
ASAP: Accelerated Short-Read Alignment on Programmable Hardware. CoRR abs/1803.02657 (2018) - [i5]Chuanhao Zhuge, Xinheng Liu, Xiaofan Zhang, Sudeep Gummadi, Jinjun Xiong, Deming Chen:
Face Recognition with Hybrid Efficient Convolution Algorithms on FPGAs. CoRR abs/1803.09004 (2018) - [i4]Di He, Boon Pang Lim, Xuesong Yang, Mark Hasegawa-Johnson, Deming Chen:
Improved ASR for Under-Resourced Languages Through Multi-Task Learning with Acoustic Landmarks. CoRR abs/1805.05574 (2018) - [i3]Junsong Wang, Qiuwen Lou, Xiaofan Zhang, Chao Zhu, Yonghua Lin, Deming Chen:
Design Flow of Accelerating Hybrid Extremely Low Bit-width Neural Network in Embedded FPGA. CoRR abs/1808.04311 (2018) - [i2]Di He, Xuesong Yang, Boon Pang Lim, Yi Liang, Mark Hasegawa-Johnson, Deming Chen:
When CTC Training Meets Acoustic Landmarks. CoRR abs/1811.02063 (2018) - 2017
- [j39]Keith A. Campbell, Wei Zuo, Deming Chen:
New advances of high-level synthesis for efficient and reliable hardware design. Integr. 58: 189-214 (2017) - [j38]Nam Sung Kim, Deming Chen, Jinjun Xiong
, Wen-mei W. Hwu:
Heterogeneous Computing Meets Near-Memory Acceleration and High-Level Synthesis in the Post-Moore Era. IEEE Micro 37(4): 10-18 (2017) - [c109]S. T. Choden Konigsmark, Deming Chen, Martin D. F. Wong
:
High-Level Synthesis for side-channel defense. ASAP 2017: 37-44 - [c108]Subhasish Mitra, Deming Chen:
ASP-DAC 2017 keynote speech I: In memory of Edward J. McCluskey: The next wave of pioneering innovations. ASP-DAC 2017: 1 - [c107]Wei Zuo, Louis-Noël Pouchet, Andrey Ayupov, Taemin Kim, Chung-Wei Lin, Shinichi Shiraishi, Deming Chen:
Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration. DAC 2017: 78:1-78:6 - [c106]Ashutosh Dhar, Deming Chen:
Efficient GPGPU Computing with Cross-Core Resource Sharing and Core Reconfiguration. FCCM 2017: 48-55 - [c105]Sitao Huang, Gowthami Jayashri Manikandan, Anand Ramachandran, Kyle Rupnow, Wen-mei W. Hwu, Deming Chen:
Hardware Acceleration of the Pair-HMM Algorithm for DNA Variant Calling. FPGA 2017: 275-284 - [c104]Subho S. Banerjee, Mohamed El-Hadedy, Jong Bin Lim, Daniel Chen, Zbigniew T. Kalbarczyk, Deming Chen, Ravishankar K. Iyer:
ASAP: Accelerated Short Read Alignment on Programmable Hardware (Abstract Only). FPGA 2017: 293-294 - [c103]Xiaofan Zhang, Xinheng Liu, Anand Ramachandran, Chuanhao Zhuge, Shibin Tang, Peng Ouyang, Zuofu Cheng, Kyle Rupnow, Deming Chen:
High-performance video content recognition with long-term recurrent convolutional network for FPGA. FPL 2017: 1-4 - [c102]Xiaofan Zhang, Anand Ramachandran, Chuanhao Zhuge, Di He, Wei Zuo, Zuofu Cheng, Kyle Rupnow, Deming Chen:
Machine learning on FPGAs to face the IoT revolution. ICCAD 2017: 819-826 - [c101]Xiaofan Zhang, Anand Ramachandran, Chuanhao Zhuge, Di He, Wei Zuo, Zuofu Cheng, Kyle Rupnow, Deming Chen:
Machine learning on FPGAs to face the IoT revolution. ICCAD 2017: 894-901 - [c100]Eric Cheng, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Keith A. Campbell, Deming Chen, Chen-Yong Cher, Hyungmin Cho, Binh Q. Le, Klas Lilja, Shahrzad Mirkhani, Kevin Skadron
, Mircea Stan
, Lukasz G. Szafaryn, Christos Vezyrtzis, Subhasish Mitra
:
Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights. ICCD 2017: 593-596 - [c99]Wen-mei W. Hwu, Izzat El Hajj, Simon Garcia De Gonzalo, Carl Pearson, Nam Sung Kim, Deming Chen, Jinjun Xiong
, Zehra Sura:
Rebooting the Data Access Hierarchy of Computing Systems. ICRC 2017: 1-4 - [c98]Di He, Zuofu Cheng, Mark Hasegawa-Johnson, Deming Chen:
Using Approximated Auditory Roughness as a Pre-Filtering Feature for Human Screaming and Affective Speech AED. INTERSPEECH 2017: 1914-1918 - [c97]Li-Wen Chang, Juan Gómez-Luna
, Izzat El Hajj, Sitao Huang, Deming Chen, Wen-mei W. Hwu:
Collaborative Computing for Heterogeneous Integrated Systems. ICPE 2017: 385-388 - [e4]Laleh Behjat, Jie Han, Miroslav N. Velev, Deming Chen:
Proceedings of the on Great Lakes Symposium on VLSI 2017, Banff, AB, Canada, May 10-12, 2017. ACM 2017, ISBN 978-1-4503-4972-7 [contents] - [i1]Di He, Boon Pang Lim, Xuesong Yang, Mark Hasegawa-Johnson, Deming Chen:
Acoustic Landmarks Contain More Information About the Phone String than Other Frames. CoRR abs/1710.09985 (2017) - 2016
- [j37]Yun Heo, Anand Ramachandran, Wen-mei W. Hwu, Jian Ma
, Deming Chen:
BLESS 2: accurate, memory-efficient and fast error correction method. Bioinform. 32(15): 2369-2371 (2016) - [j36]Deming Chen, Jason Cong, Swathi T. Gurumani, Wen-mei W. Hwu, Kyle Rupnow
, Zhiru Zhang:
Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs. IET Cyper-Phys. Syst.: Theory & Appl. 1(1): 70-77 (2016) - [j35]Yangbing Wu
, Jianfeng Zhao, Deming Chen, Donghui Guo:
Modeling of Gaussian Network-Based Reconfigurable Network-on-Chip Designs. IEEE Trans. Computers 65(7): 2134-2142 (2016) - [j34]Sven Tenzing Choden Konigsmark, Deming Chen, Martin D. F. Wong
:
PolyPUF: Physically Secure Self-Divergence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(7): 1053-1066 (2016) - [j33]Yun Liang, Muhammad Teguh Satria, Kyle Rupnow
, Deming Chen:
An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(7): 1165-1178 (2016) - [j32]Ying Chen, Tan Nguyen, Yao Chen
, Swathi T. Gurumani, Yun Liang, Kyle Rupnow
, Jason Cong, Wen-mei W. Hwu, Deming Chen:
FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2032-2045 (2016) - [j31]Deming Chen:
Introduction. ACM Trans. Reconfigurable Technol. Syst. 9(4): 28:1-28:2 (2016) - [j30]Morteza Gholipour, Ying-Yu Chen, Amit Sangai, Nasser Masoumi, Deming Chen:
Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 650-663 (2016) - [j29]Yao Chen
, Swathi T. Gurumani, Yun Liang, Guofeng Li, Donghui Guo, Kyle Rupnow
, Deming Chen:
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2220-2233 (2016) - [c96]Zelei Sun, Keith A. Campbell, Wei Zuo, Kyle Rupnow, Swathi T. Gurumani, Frederic Doucet, Deming Chen:
Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis. ASP-DAC 2016: 218-225 - [c95]Ying-Yu Chen, Morteza Gholipour, Deming Chen:
Flexible transition metal dichalcogenide field-effect transistors: A circuit-level simulation study of delay and power under bending, process variation, and scaling. ASP-DAC 2016: 761-768 - [c94]Keith A. Campbell, Leon He, Liwei Yang, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation. DAC 2016: 7:1-7:6 - [c93]S. T. Choden Konigsmark, Deming Chen, Martin D. F. Wong
:
Information dispersion for trojan defense through high-level synthesis. DAC 2016: 87:1-87:6 - [c92]Muhammad Teguh Satria, Swathi T. Gurumani, Wang Zheng, Keng Peng Tee, Augustine Koh, Pan Yu, Kyle Rupnow, Deming Chen:
Real-time system-level implementation of a telepresence robot using an embedded GPU platform. DATE 2016: 1445-1448 - [c91]Liwei Yang, Swathi T. Gurumani, Deming Chen, Kyle Rupnow:
AutoSLIDE: Automatic Source-Level Instrumentation and Debugging for HLS. FCCM 2016: 127-130 - [c90]Gowthami Jayashri Manikandan, Sitao Huang, Kyle Rupnow, Wen-mei W. Hwu, Deming Chen:
Acceleration of the Pair-HMM Algorithm for DNA Variant Calling. FCCM 2016: 137 - [c89]Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
FCUDA-SoC: Platform Integration for Field-Programmable SoC with the CUDA-to-FPGA Compiler. FPGA 2016: 5-14 - [c88]Xinheng Liu, Yao Chen
, Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
High Level Synthesis of Complex Applications: An H.264 Video Decoder. FPGA 2016: 224-233 - [c87]Liwei Yang, Swathi T. Gurumani, Suhaib A. Fahmy, Deming Chen, Kyle Rupnow:
Automated Verification Code Generation in HLS Using Software Execution Traces (Abstract Only). FPGA 2016: 278 - [c86]Warren Kemmerer, Wei Zuo, Deming Chen:
Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design. ICCAD 2016: 79 - [c85]Tan Nguyen, Yao Chen
, Kyle Rupnow, Swathi T. Gurumani, Deming Chen:
SoC, NoC and Hierarchical Bus Implementations of Applications on FPGAs Using the FCUDA Flow. ISVLSI 2016: 661-666 - [e3]Deming Chen, Jonathan W. Greene:
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 21-23, 2016. ACM 2016, ISBN 978-1-4503-3856-1 [contents] - 2015
- [j28]Zhiru Zhang
, Deming Chen, Steve Dai, Keith A. Campbell:
High-level Synthesis for Low-power Design. IPSJ Trans. Syst. LSI Des. Methodol. 8: 12-25 (2015) - [j27]Yun Liang, Xiaolong Xie, Guangyu Sun, Deming Chen:
An Efficient Compiler Framework for Cache Bypassing on GPUs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(10): 1677-1690 (2015) - [j26]Yun Liang, Huynh Phung Huynh, Kyle Rupnow
, Rick Siow Mong Goh, Deming Chen:
Efficient GPU Spatial-Temporal Multitasking. IEEE Trans. Parallel Distributed Syst. 26(3): 748-760 (2015) - [c84]Liwei Yang, Yao Chen
, Wei Zuo, Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
System-level design solutions: Enabling the IoT explosion. ASICON 2015: 1-4 - [c83]Keith A. Campbell, David Lin, Subhasish Mitra
, Deming Chen:
Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principles. DAC 2015: 53:1-53:6 - [c82]Ying-Yu Chen, Zelei Sun, Deming Chen:
A SPICE model of flexible transition metal dichalcogenide field-effect transistors. DAC 2015: 140:1-140:6 - [c81]Keith A. Campbell, Pranay Vissa, David Z. Pan, Deming Chen:
High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths. DAC 2015: 161:1-161:6 - [c80]Chunan Wei, Ashutosh Dhar, Deming Chen:
A scalable and high-density FPGA architecture with multi-level phase change memory. DATE 2015: 1365-1370 - [c79]Anand Ramachandran, Yun Heo, Wen-mei W. Hwu, Jian Ma, Deming Chen:
FPGA accelerated DNA error correction. DATE 2015: 1371-1376 - [c78]Liwei Yang, Swathi T. Gurumani, Deming Chen, Kyle Rupnow:
Behavioral-level IP integration in high-level synthesis. FPT 2015: 172-175 - [c77]Liwei Yang, Magzhan Ikram, Swathi T. Gurumani, Suhaib A. Fahmy, Deming Chen, Kyle Rupnow:
JIT trace-based verification for high-level synthesis. FPT 2015: 228-231 - [c76]Miodrag Potkonjak, Deming Chen, Priyank Kalla, Steven P. Levitan:
DA Vision 2015: From Here to Eternity. ICCAD 2015: 271-277 - [c75]Wei Zuo, Warren Kemmerer, Jong Bin Lim, Louis-Noël Pouchet, Andrey Ayupov, Taemin Kim, Kyungtae Han, Deming Chen:
A Polyhedral-based SystemC Modeling and Generation Framework for Effective Low-power Design Space Exploration. ICCAD 2015: 357-364 - [c74]Chen-Hsuan Lin, Subhendu Roy, Chun-Yao Wang, David Z. Pan, Deming Chen:
CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction. ICCD 2015: 236-243 - [e2]George A. Constantinides, Deming Chen:
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 22-24, 2015. ACM 2015, ISBN 978-1-4503-3315-3 [contents] - 2014
- [j25]Yun Heo, Xiaolong Wu, Deming Chen, Jian Ma
, Wen-mei W. Hwu:
BLESS: Bloom filter-based error correction solution for high-throughput sequencing reads. Bioinform. 30(10): 1354-1362 (2014) - [j24]Hongyin Luo, Shaojun Wei, Deming Chen, Donghui Guo:
Hybrid circuit-switched network for on-chip communication in large-scale chip-multiprocessors. J. Parallel Distributed Comput. 74(9): 2818-2830 (2014) - [j23]Hongbin Zheng, Swathi T. Gurumani, Liwei Yang, Deming Chen, Kyle Rupnow
:
High-Level Synthesis With Behavioral-Level Multicycle Path Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1832-1845 (2014) - [c73]S. T. Choden Konigsmark, Leslie Hwang, Deming Chen, Martin D. F. Wong
:
CNPUF: A Carbon Nanotube-based Physically Unclonable Function for secure low-energy hardware design. ASP-DAC 2014: 73-78 - [c72]Yi Liang, Deming Chen:
Fast large-scale optimal power flow analysis for smart grid through network reduction. ASP-DAC 2014: 373-378 - [c71]S. T. Choden Konigsmark, Leslie K. Hwang, Deming Chen, Martin D. F. Wong
:
System-of-PUFs: Multilevel security for embedded systems. CODES+ISSS 2014: 27:1-27:10 - [c70]Yi Liang, Deming Chen:
ClusRed: Clustering and Network Reduction Based Probabilistic Optimal Power Flow Analysis for Large-Scale Smart Grids. DAC 2014: 188:1-188:6 - [c69]Chen-Hsuan Lin, Lu Wan, Deming Chen:
C-Mine: Data Mining of Logic Common Cases for Low Power Synthesis of Better-Than-Worst-Case Designs. DAC 2014: 205:1-205:6 - [c68]Morteza Gholipour, Ying-Yu Chen, Amit Sangai, Deming Chen:
Highly accurate SPICE-compatible modeling for single- and double-gate GNRFETs with studies on technology scaling. DATE 2014: 1-6 - [c67]Swathi T. Gurumani, Jacob Tolar, Yao Chen
, Yun Liang, Kyle Rupnow
, Deming Chen:
Integrated CUDA-to-FPGA Synthesis with Network-on-Chip. FCCM 2014: 21-24 - [c66]Hongbin Zheng, Swathi T. Gurumani, Kyle Rupnow
, Deming Chen:
Fast and effective placement and routing directed high-level synthesis for FPGAs. FPGA 2014: 1-10 - [c65]Peng Li
, Louis-Noël Pouchet, Deming Chen, Jason Cong:
Transformations for throughput optimization in high-level synthesis (abstract only). FPGA 2014: 245 - [c64]Wei Zuo, Hongbin Zheng, Swathi T. Gurumani, Kyle Rupnow
, Deming Chen:
New solutions for system-level and high-level synthesis (Invited paper). ISIC 2014: 71-74 - [c63]Renato Mancuso
, Prakalp Srivastava, Deming Chen, Marco Caccamo:
A hardware architecture to deploy complex multiprocessor scheduling algorithms. RTCSA 2014: 1-10 - [c62]Sizhao Li
, Shan Lin, Deming Chen, W. Eric Wong, Donghui Guo:
Analysis of System Reliability for Cache Coherence Scheme in Multi-processor. SERE (Companion) 2014: 247-251 - 2013
- [j22]Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu:
Efficient compilation of CUDA kernels for high-performance computing on FPGAs. ACM Trans. Embed. Comput. Syst. 13(2): 25:1-25:26 (2013) - [j21]Tan Yan, Qiang Ma, Scott Chilstedt, Martin D. F. Wong
, Deming Chen:
A routing algorithm for graphene nanoribbon circuit. ACM Trans. Design Autom. Electr. Syst. 18(4): 61:1-61:18 (2013) - [c61]Swathi T. Gurumani, Hisham Cholakkal
, Yun Liang, Kyle Rupnow
, Deming Chen:
High-level synthesis of multiple dependent CUDA kernels on FPGA. ASP-DAC 2013: 305-312 - [c60]Yun Liang, Zheng Cui, Kyle Rupnow
, Deming Chen:
Register and thread structure optimization for GPUs. ASP-DAC 2013: 461-466 - [c59]Wei Zuo, Peng Li
, Deming Chen, Louis-Noël Pouchet, Shunan Zhong, Jason Cong:
Improving polyhedral code generation for high-level synthesis. CODES+ISSS 2013: 15:1-15:10 - [c58]Alexandros Papakonstantinou, Deming Chen, Wen-mei W. Hwu, Jason Cong, Yun Liang:
Throughput-oriented kernel porting onto FPGAs. DAC 2013: 11:1-11:10 - [c57]Ying-Yu Chen, Artem Rogachev, Amit Sangai, Giuseppe Iannaccone, Gianluca Fiori, Deming Chen:
A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation. DATE 2013: 1789-1794 - [c56]Wei Zuo, Yun Liang, Peng Li
, Kyle Rupnow
, Deming Chen, Jason Cong:
Improving high level synthesis optimization opportunity through polyhedral transformations. FPGA 2013: 9-18 - [c55]Hongbin Zheng, Swathi T. Gurumani, Liwei Yang, Deming Chen, Kyle Rupnow
:
High-level synthesis with behavioral level multi-cycle path analysis. FPL 2013: 1-8 - [c54]Xiaolong Xie, Yun Liang, Guangyu Sun, Deming Chen:
An efficient compiler framework for cache bypassing on GPUs. ICCAD 2013: 516-523 - [c53]Ying-Yu Chen, Amit Sangai, Morteza Gholipour, Deming Chen:
Graphene nano-ribbon field-effect transistors as future low-power devices. ISLPED 2013: 151-156 - [c52]Ying-Yu Chen, Amit Sangai, Morteza Gholipour, Deming Chen:
Schottky-barrier-type Graphene Nano-Ribbon Field-Effect Transistors: A study on compact modeling, process variation, and circuit performance. NANOARCH 2013: 82-88 - [c51]Deming Chen:
Optimizations in GPU: Smart compilers and core-level reconfiguration. SLIP 2013: 1 - 2012
- [j20]Xiaolong Wu, Yun Heo, Izzat El Hajj, Wen-mei W. Hwu, Deming Chen, Jian Ma
:
TIGER: tiled iterative genome assembler. BMC Bioinform. 13(S-19): S18 (2012) - [j19]Lu Wan, Chen Dong, Deming Chen
:
A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance. Int. J. Reconfigurable Comput. 2012: 163542:1-163542:17 (2012) - [j18]Deming Chen, Kiyoung Choi, Philippe Coussy, Yuan Xie, Zhiru Zhang
:
ESL Design Methodology. J. Electr. Comput. Eng. 2012: 358281:1-358281:2 (2012) - [j17]Yun Liang, Kyle Rupnow
, Yinan Li, Dongbo Min, Minh N. Do
, Deming Chen:
High-Level Synthesis: Productivity, Performance, and Software Constraints. J. Electr. Comput. Eng. 2012: 649057:1-649057:14 (2012) - [j16]Lu Wan, Deming Chen:
Analysis of Digital Circuit Dynamic Behavior With Timed Ternary Decision Diagrams for Better-Than-Worst-Case Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(5): 662-675 (2012) - [c50]Yun Liang, Zheng Cui, Shengkui Zhao, Kyle Rupnow, Yihao Zhang, Douglas L. Jones, Deming Chen:
Real-time implementation and performance optimization of 3D sound localization on GPUs. DATE 2012: 832-835 - [c49]Zheng Cui, Yun Liang, Kyle Rupnow
, Deming Chen:
An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization. IPDPS 2012: 83-94 - [c48]Lu Wan, Deming Chen:
CCP: common case promotion for improved timing error resilience with energy efficiency. ISLPED 2012: 135-140 - [c47]Wenxun Huang, Yujuan Quan, Deming Chen:
Improving broadcast efficiency in wireless sensor network time synchronization protocols. SLIP 2012: 48-55 - 2011
- [c46]Kyle Rupnow
, Yun Liang, Yinan Li, Deming Chen:
A study of high-level synthesis: Promises and challenges. ASICON 2011: 1102-1105 - [c45]Tan Yan, Qiang Ma, Scott Chilstedt, Martin D. F. Wong
, Deming Chen:
Routing with graphene nanoribbons. ASP-DAC 2011: 323-329 - [c44]Chi-Chen Peng, Chen Dong, Deming Chen:
SETmap: A soft error tolerant mapping algorithm for FPGA designs with low power. ASP-DAC 2011: 388-393 - [c43]Alexandros Papakonstantinou, Yun Liang, John A. Stratton, Karthik Gururaj, Deming Chen, Wen-mei W. Hwu, Jason Cong:
Multilevel Granularity Parallelism Synthesis on FPGAs. FCCM 2011: 178-185 - [c42]Kyle Rupnow
, Yun Liang, Yinan Li, Dongbo Min, Minh N. Do
, Deming Chen:
High level synthesis of stereo matching: Productivity, performance, and software constraints. FPT 2011: 1-8 - [c41]Artem Rogachev, Lu Wan, Deming Chen:
Temperature aware statistical static timing analysis. ICCAD 2011: 103-110 - [c40]Chen Dong, Chen Chen, Subhasish Mitra, Deming Chen:
Architecture and performance evaluation of 3D CMOS-NEM FPGA. SLIP 2011: 1-8 - [e1]Janet Meiling Wang, Deming Chen:
2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1240-1 [contents] - 2010
- [j15]Shoaib Akram, Alexandros Papakonstantinou, Rakesh Kumar, Deming Chen:
A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors. Int. J. Reconfigurable Comput. 2010: 205852:1-205852:22 (2010) - [j14]Quang Dinh, Deming Chen, Martin D. F. Wong
:
A Routing Approach to Reduce Glitches in Low Power FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 235-240 (2010) - [j13]Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li, Chi-Chen Peng:
Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1709-1722 (2010) - [j12]Gregory Lucas, Chen Dong, Deming Chen:
Variation-Aware Placement With Multi-Cycle Statistical Timing Analysis for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1818-1822 (2010) - [j11]Deming Chen, Jason Cong, Yiping Fan, Lu Wan:
LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 564-577 (2010) - [c39]Quang Dinh, Deming Chen, Martin D. F. Wong
:
Dynamic power estimation for deep submicron circuits with process variation. ASP-DAC 2010: 587-592 - [c38]Ying-Yu Chen, Chen Dong, Deming Chen:
Clock tree synthesis under aggressive buffer insertion. DAC 2010: 86-89 - [c37]Gregory Lucas, Chen Dong, Deming Chen:
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis. FPGA 2010: 177-180 - [c36]Gregory Lucas, Deming Chen:
Variation-aware layout-driven scheduling for performance yield optimization. ICCAD 2010: 17-24 - [c35]Lu Wan, Deming Chen:
Analysis of circuit dynamic behavior with timed ternary decision diagram. ICCAD 2010: 516-523 - [c34]Quang Dinh, Deming Chen, Martin D. F. Wong
:
BDD-based circuit restructuring for reducing dynamic power. ICCD 2010: 548-554
2000 – 2009
- 2009
- [j10]Scott Chilstedt, Chen Dong, Deming Chen:
Design and Evaluation of a Carbon Nanotube-Based Programmable Architecture. Int. J. Parallel Program. 37(4): 389-416 (2009) - [j9]Deming Chen, Scott Cromar:
An Optimal Resource Binding Algorithm with Inter-Transition Switching Activities for Low Power. J. Low Power Electron. 5(4): 454-463 (2009) - [j8]Hao Li, Dae Hyun Kwon, Deming Chen, Yun Chiu
:
A Fast Digital Predistortion Algorithm for Radio-Frequency Power Amplifier Linearization With Loop Delay Compensation. IEEE J. Sel. Top. Signal Process. 3(3): 374-383 (2009) - [c33]Gregory Lucas, Scott Cromar, Deming Chen:
FastYield: variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization. ASP-DAC 2009: 61-66 - [c32]Scott Cromar, Jaeho Lee, Deming Chen:
FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation. DAC 2009: 838-843 - [c31]Chen Dong, Scott Chilstedt, Deming Chen:
Reconfigurable circuit design with nanomaterials. DATE 2009: 442-447 - [c30]Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger:
CMOS vs Nano: comrades or rivals? FPGA 2009: 121-122 - [c29]Chen Dong, Scott Chilstedt, Deming Chen:
FPCNA: a field programmable carbon nanotube array. FPGA 2009: 161-170 - [c28]Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig B. Zilles:
Blueshift: Designing processors for timing speculation from the ground up. HPCA 2009: 213-224 - [c27]Lu Wan, Deming Chen:
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior. ICCAD 2009: 172-179 - [c26]Chun He, Alexandros Papakonstantinou, Deming Chen:
A novel SoC architecture on FPGA for ultra fast face detection. ICCD 2009: 412-418 - [c25]Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu:
High-performance CUDA kernel execution on FPGAs. ICS 2009: 515-516 - [c24]Quang Dinh, Deming Chen, Martin D. F. Wong
:
A routing approach to reduce glitches in low power FPGAs. ISPD 2009: 99-106 - [c23]Chen Dong, Scott Chilstedt, Deming Chen:
Variation Aware Routing for Three-Dimensional FPGAs. ISVLSI 2009: 298-303 - [c22]Shoaib Akram, Rakesh Kumar, Deming Chen:
Workload adaptive shared memory multicore processors with reconfigurable interconnects. SASP 2009: 7-14 - [c21]Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu:
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs. SASP 2009: 35-42 - [p1]Deming Chen:
Design Automation for Microelectronics. Handbook of Automation 2009: 653-670 - 2008
- [j7]Lei Cheng, Deming Chen, Martin D. F. Wong
:
DDBDD: Delay-Driven BDD Synthesis for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1203-1213 (2008) - [j6]Lei Cheng, Deming Chen, Martin D. F. Wong
:
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. ACM Trans. Design Autom. Electr. Syst. 13(2): 34:1-34:15 (2008) - [c20]Shoaib Akram, Scott Cromar, Gregory Lucas, Alexandros Papakonstantinou, Deming Chen:
VEBoC: Variation and error-aware design for billions of devices on a chip. ASP-DAC 2008: 803-808 - [c19]Quang Dinh, Deming Chen, Martin D. F. Wong
:
Efficient ASIP design for configurable processors with fine-grained resource sharing. FPGA 2008: 99-106 - [c18]Alexandros Papakonstantinou, Deming Chen, Wen-mei W. Hwu:
Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor. SASP 2008: 20-25 - 2007
- [j5]Chen Dong, Deming Chen, S. Haruehanroengra, Wei Wang:
3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS/Nanomaterial Hybrid Digital Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(11): 2489-2501 (2007) - [c17]Deming Chen, Jason Cong, Yiping Fan, Zhiru Zhang
:
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. ASP-DAC 2007: 529-534 - [c16]Lei Cheng, Deming Chen, Martin D. F. Wong
:
GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches. DAC 2007: 318-323 - [c15]Lei Cheng, Deming Chen, Martin D. F. Wong
:
DDBDD: Delay-Driven BDD Synthesis for FPGAs. DAC 2007: 910-915 - [c14]Lei Cheng, Deming Chen, Martin D. F. Wong
, Mike Hutton, Jason Govig:
Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains. ICCAD 2007: 370-375 - [c13]Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei Wang:
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture. ICCAD 2007: 758-764 - 2006
- [j4]Deming Chen, Jason Cong, Peichen Pan:
FPGA Design Automation: A Survey. Found. Trends Electron. Des. Autom. 1(3) (2006) - [j3]Deming Chen, Jason Cong, Junjuan Xu:
Optimal simultaneous module and multivoltage assignment for low power. ACM Trans. Design Autom. Electr. Syst. 11(2): 362-386 (2006) - [c12]Lei Cheng, Liang Deng, Deming Chen, Martin D. F. Wong
:
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. DAC 2006: 117-120 - [c11]Joey Y. Lin, Deming Chen, Jason Cong:
Optimal simultaneous mapping and clustering for FPGA delay optimization. DAC 2006: 472-477 - [c10]Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu:
Optimality study of resource binding with multi-Vdds. DAC 2006: 580-585 - 2005
- [j2]Fei Li, Yizhou Lin, Lei He, Deming Chen, Jason Cong:
Power modeling and characteristics of field programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1712-1724 (2005) - [c9]Deming Chen, Jason Cong, Junjuan Xu:
Optimal module and voltage assignment for low-power. ASP-DAC 2005: 850-855 - [c8]Ren Wang, Deming Chen, Qingquan Qian:
Research of double loop optical fiber self-cicatrized network based on Neuron3150. ISADS 2005: 352-355 - 2004
- [c7]Deming Chen, Jason Cong:
Register binding and port assignment for multiplexer optimization. ASP-DAC 2004: 68-73 - [c6]Deming Chen, Jason Cong, Fei Li, Lei He:
Low-power technology mapping for FPGA architectures with dual supply voltages. FPGA 2004: 109-117 - [c5]Deming Chen, Jason Cong:
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs. ICCAD 2004: 752-759 - [c4]Deming Chen, Jason Cong:
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. ISLPED 2004: 70-73 - 2003
- [j1]Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang:
Performance-driven mapping for CPLD architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1424-1431 (2003) - [c3]Fei Li, Deming Chen, Lei He, Jason Cong:
Architecture evaluation for power-efficient FPGAs. FPGA 2003: 175-184 - [c2]Deming Chen, Jason Cong, Yiping Fan:
Low-power high-level synthesis for FPGA architectures. ISLPED 2003: 134-139 - 2001
- [c1]Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang:
Performance-driven mapping for CPLD architectures. FPGA 2001: 39-47
Coauthor Index
aka: Rama Krishna Sai Subrahmanyam Gorthi
aka: Gorthi R. K. Sai Subrahmanyam
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