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ORCIDSimon Jones 0001
Person information
- affiliation: Loughborough University of Technology, Department of Electronic and Electrical Engineering, Leicestershire, UK
Other persons with the same name
- Simon Jones — disambiguation page
- Simon Jones 0002
![[0000-0002-8267-5647]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0002-8267-5647")
(aka: Simon Andrew Jones) — New York University, NYU School of Medicine, NY, USA (and 2 more)
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Journal Articles
- 2005
[j13]René Cumplido, Simon R. Jones, Roger Goodall, Stephen Bateman:
A high-performance processor for embedded real-time control. IEEE Trans. Control. Syst. Technol. 13(3): 485-492 (2005)- 2004
- [j12]Xianhong Xu, Simon Jones:
Code Compression for the Embedded arm/Thumb Processor. Int. J. Comput. 3(2): 7-12 (2004) - 2003
- [j11]José Luis Núñez, Simon Jones:
Gbit/s lossless data compression hardware. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 499-510 (2003) - 2002
- [j10]José Luis Núñez, Simon Jones, Stephen Bateman:
X-Matchpro: a High Performance Full-duplex lossless Data Compressor on a ProASIC FPGA. Int. J. Comput. 1(1): 50-55 (2002) - 2000
- [j9]Simon R. Jones, Ray Meddis, Seow Chuan Lim, Arthur Robert Temple:
Toward a digital neuromorphic pitch extraction system. IEEE Trans. Neural Networks Learn. Syst. 11(4): 978-987 (2000) - 1999
- [j8]Morten Kjelsø, Mark Gooch, Simon Jones:
Performance evaluation of computer architectures with main memory data compression. J. Syst. Archit. 45(8): 571-590 (1999) - 1998
- [j7]J. Yeandel, D. Thulborn, Simon Jones:
The Design and Implementation of an On-Line Testable UART. J. Electron. Test. 12(3): 187-198 (1998) - 1995
- [j6]David C. J. Naylor, Simon Jones, David Myers:
Backpropagation in linear arrays-a performance analysis and optimization. IEEE Trans. Neural Networks 6(3): 583-595 (1995) - 1994
- [j5]Simon Jones:
Digital BiCMOS Integrated Circuit Design: Sherif H K Embabi, A. Bellaouar and Mohamed I Elmasry Kluwer Academic, Dordrecht, The Netherlands (1992) ISBN 0 7923 9276 0, £62.50, pp 432. Microprocess. Microsystems 18(1): 55 (1994) - [j4]Simon R. Jones, Karl M. Sammut, Jamie Hunter:
Learning in linear systolic neural network engines: analysis and implementation. IEEE Trans. Neural Networks 5(4): 584-593 (1994) - [j3]David C. J. Naylor, Simon Jones:
A Performance Model for Multilayer Neural Networks in Linear Arrays. IEEE Trans. Parallel Distributed Syst. 5(12): 1322-1328 (1994) - 1993
- [j2]David C. J. Naylor, Simon Jones, David Myers, John Vincent:
Neural Network Feature Detector For Real-Time Video Signal Processing. Int. J. Neural Syst. 4(4): 337-349 (1993) - 1988
- [j1]Simon R. Jones, Ian P. Jalowiecki, Stephen J. Hedge, R. Mike Lea:
A 9-kbit associative memory for high-speed parallel processing applications. IEEE J. Solid State Circuits 23(2): 543-548 (1988)
Conference and Workshop Papers
- 2002
- [c14]Dario L. Sancho-Pradel, Simon R. Jones, Roger Goodall:
System on programmable chip for real-time control implementations. FPT 2002: 276-283 - [c13]José Luis Núñez, Simon Jones:
Lossless data compression programmable hardware for high-speed data networks. FPT 2002: 290-293 - 2001
- [c12]José Luis Núñez, Claudia Feregrino, Simon R. Jones, Stephen Bateman:
X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor. FPL 2001: 613-617 - [c11]Riad Stefo, José Luis Núñez, Claudia Feregrino, Sudipta Mahapatra, Simon R. Jones:
FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding. FPL 2001: 643-647 - 1999
- [c10]José Luis Núñez, Claudia Feregrino, Simon R. Jones, Stephen Bateman:
The X-MatchLITE FPGA-Based Data Compressor. EUROMICRO 1999: 1126-1132 - [c9]José Luis Núñez, Claudia Feregrino, Stephen Bateman, Simon R. Jones:
The X-MatchLITE FPGA-Based Data Compressor. FPGA 1999: 255 - 1997
- [c8]Seow Chuan Lim, Arthur Robert Temple, Simon Jones, Ray Meddis:
VHDL-based design of biologically inspired pitch detection system. ICNN 1997: 922-927 - [c7]Seow Chuan Lim, Arthur Robert Temple, Simon R. Jones, Ray Meddis:
Biologically Inspired Pitch Detection System. ICONIP (1) 1997: 654-657 - [c6]J. Yeandel, D. Thulborn, Simon Jones:
An on-line testable UART implemented using IFIS. VTS 1997: 344-349 - 1996
- [c5]Morten Kjelsø, Mark Gooch, Simon Jones:
Design and Performance of a Main Memory Hardware Data Compressor. EUROMICRO 1996: 423-430 - 1995
- [c4]Eckhard Grass, Simon Jones:
Asynchronous circuits based on multiple localised current-sensing completion detection. ASYNC 1995: 170- - [c3]Morten Kjelsø, Simon Jones:
Memory Management in Flash-Memory Disks with Data Compression. IWMM 1995: 399-413 - 1993
- [c2]Simon Jones:
Design and implementation of video-rate real-time systems incorporating neural networks: experiments and experience. ANNES 1993 - [c1]David C. J. Naylor, Simon Jones:
A Model Based Approach to the Performance Analysis of Multi-Layer Networks Realised in Linear Systolic Arrays. IWANN 1993: 459-464
Coauthor Index
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