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2020 – today
- 2021
[c34]David R. Ditzel, Roger Espasa, Nivard Aymerich, Allen Baum, Tom Berg, Jim Burr, Eric Hao, Jayesh Iyer, Miquel Izquierdo, Shankar Jayaratnam, Darren Jones, Chris Klingner, Jin Kim, Stephen Lee, Marc Lupon, Grigorios Magklis, Bojan Maric, Rajib Nath, Mike Neilly, J. Duane Northcutt, Bill Orner, Jose Renau, Gerard Reves, Xavier Reves, Tom Riordan, Pedro Sanchez, Sridhar Samudrala, Guillem Sole, Raymond Tang, Tommy Thorn, Francisco Torres, Sebastia Tortella, Daniel Yau:
Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip. HCS 2021: 1-23
2010 – 2019
- 2010
- [j9]Jordi Roca, Victor Moya Del Barrio, Carlos González, Vicente Escandell, Albert Murciego, Agustín Fernández, Roger Espasa:
A SIMD-efficient 14 instruction shader program for high-throughput microtriangle rasterization. Vis. Comput. 26(6-8): 707-719 (2010) - [c33]Roger Espasa:
Larrabee: A Many-Core Intel Architecture for Visual Computing. HiPEAC 2010: 2
2000 – 2009
- 2009
- [j8]Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Pradeep Dubey, Stephen Junkins, Adam T. Lake, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Michael Abrash, Jeremy Sugerman, Pat Hanrahan:
Larrabee: A Many-Core x86 Architecture for Visual Computing. IEEE Micro 29(1): 10-21 (2009) - 2008
- [j7]Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam T. Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Pat Hanrahan:
Larrabee: a many-core x86 architecture for visual computing. ACM Trans. Graph. 27(3): 18 (2008) - 2006
- [c32]Jordi Roca, Victor Moya Del Barrio, Carlos González, Chema Solis, Agustín Fernández, Roger Espasa:
Workload Characterization of 3D Games. IISWC 2006: 17-26 - [c31]Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustín Fernández, Roger Espasa:
ATTILA: a cycle-level execution-driven simulator for modern GPU architectures. ISPASS 2006: 231-241 - 2005
- [j6]André Seznec, Roger Espasa:
Conflict-Free Accesses to Strided Vectors on a Banked Cache. IEEE Trans. Computers 54(7): 913-196 (2005) - [c30]Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustín Fernández, Roger Espasa:
A Single (Unified) Shader GPU Microarchitecture for Embedded Systems. HiPEAC 2005: 286-301 - [c29]Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustín Fernández, Roger Espasa:
Shader Performance Analysis on a Modern GPU Architecture. MICRO 2005: 355-364 - 2004
- [c28]Manel Fernández, Roger Espasa:
Link-Time Optimization Techniques for Eliminating Conditional Branch Redundancies. Interaction between Compilers and Computer Architectures 2004: 87-96 - [c27]Manel Fernández, Roger Espasa:
Link-Time Path-Sensitive Memory Redundancy Elimination. HPCA 2004: 300-310 - 2003
- [j5]Manel Fernández, Roger Espasa, Saumya K. Debray:
Load redundancy elimination on executable code. Concurr. Comput. Pract. Exp. 15(10): 979-997 (2003) - [j4]Francisca Quintana
, Jesús Corbal, Roger Espasa, Mateo Valero:
A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications. Theory Comput. Syst. 36(5): 575-593 (2003) - 2002
- [j3]Joel S. Emer, Pritpal S. Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan L. Binkert, Roger Espasa, Toni Juan:
Asim: A Performance Model Framework. Computer 35(2): 68-76 (2002) - [c26]Manel Fernández, Roger Espasa:
Speculative Alias Analysis for Executable Code. IEEE PACT 2002: 222-231 - [c25]Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec:
Tarantula: A Vector Extension to the Alpha Architecture. ISCA 2002: 281-292 - [c24]Jesús Corbal, Roger Espasa, Mateo Valero:
Three-dimensional memory vectorization for high bandwidth media memory systems. MICRO 2002: 149-160 - 2001
- [c23]Jesús Corbal, Roger Espasa, Mateo Valero:
On the Efficiency of Reductions in µ-SIMD Media Extensions. IEEE PACT 2001: 83-94 - [c22]Manel Fernández, Roger Espasa, Saumya K. Debray:
Load Redundancy Elimination on Executable Code. Euro-Par 2001: 221-229 - [c21]Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec:
Topic 08+13: Instruction-Level Parallelism and Computer Architecture. Euro-Par 2001: 385 - [c20]Jesús Corbal, Roger Espasa, Mateo Valero:
DLP + TLP Processors for the Next Generation of Media Workloads. HPCA 2001: 219-228 - [c19]Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero:
A cost effective architecture for vectorizable numerical and multimedia applications. SPAA 2001: 103-112
1990 – 1999
- 1999
- [j2]Roger Espasa, Mateo Valero:
A Simulation Study of Decoupled Vector Architectures. J. Supercomput. 14(2): 124-152 (1999) - [c18]Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero:
Adding a vector unit to a superscalar processor. International Conference on Supercomputing 1999: 1-10 - [c17]Jesús Corbal, Roger Espasa, Mateo Valero:
Exploiting a New Level of DLP in Multimedia Applications. MICRO 1999: 72-79 - [c16]Jesús Corbal, Roger Espasa, Mateo Valero:
MOM: a Matrix SIMD Instruction Set Architecture for Multimedia Applications. SC 1999: 15 - 1998
- [c15]Jesús Corbal, Roger Espasa, Mateo Valero:
Command Vector Memory Systems: High Performance at Low Cost. IEEE PACT 1998: 68- - [c14]Luis Villa, Roger Espasa, Mateo Valero:
A Performance Study of Out-of-order Vector Architectures and Short Registers. International Conference on Supercomputing 1998: 37-44 - [c13]Roger Espasa, Mateo Valero, James E. Smith:
Vector Architectures: Past, Present and Future. International Conference on Supercomputing 1998: 425-432 - [c12]Alexandre Farcy, Olivier Temam, Roger Espasa, Toni Juan:
Dataflow Analysis of Branch Mispredictions and Its Application to Early Resolution of Branch Outcomes. MICRO 1998: 59-68 - [c11]Francisca Quintana, Roger Espasa, Mateo Valero:
A case for merging the ILP and DLP paradigms. PDP 1998: 217-224 - [c10]Luis Villa, Roger Espasa, Mateo Valero:
Effective usage of vector registers in decoupled vector architectures. PDP 1998: 495-501 - [c9]Luis Villa, Roger Espasa, Mateo Valero:
Registers Size Influence on Vector Architectures. VECPAR 1998: 439-451 - [c8]Francisca Quintana, Roger Espasa, Mateo Valero:
An ISA Comparison Between Superscalar and Vector Processors. VECPAR 1998: 548-560 - 1997
- [j1]Roger Espasa, Mateo Valero:
Exploiting instruction- and data-level parallelism. IEEE Micro 17(5): 20-27 (1997) - [c7]Luis Villa, Roger Espasa, Mateo Valero:
Effective Usage of Vector Registers in Advanced Vector Architectures. IEEE PACT 1997: 250-260 - [c6]Roger Espasa, Mateo Valero:
Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance. HiPC 1997: 350-357 - [c5]Roger Espasa, Mateo Valero:
Multithreaded Vector Architectures. HPCA 1997: 237-248 - [c4]Roger Espasa, Mateo Valero:
A Victim Cache for Vector Registers. International Conference on Supercomputing 1997: 293-300 - [c3]Roger Espasa, Mateo Valero, James E. Smith:
Out-of-Order Vector Architectures. MICRO 1997: 160-170 - 1996
- [c2]Roger Espasa, Mateo Valero:
Decoupled Vector Architectures. HPCA 1996: 281-290 - 1995
- [c1]Roger Espasa, Mateo Valero, David A. Padua, Marta Jiménez, Eduard Ayguadé:
Quantitative analysis of vector code. PDP 1995: 452-463
Coauthor Index
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