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2020 – today
- 2020
[c25]Lukás Kekely, Jakub Cabal, Viktor Pus, Jan Korenek:
Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs. DSD 2020: 49-56
2010 – 2019
- 2018
- [j2]Pavel Benácek, Viktor Pus, Hana Kubátová, Tomás Cejka
:
P4-To-VHDL: Automatic generation of high-speed input and output network blocks. Microprocess. Microsystems 56: 22-33 (2018) - [c24]Jakub Cabal, Pavel Benácek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek:
Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. FPGA 2018: 249-258 - [c23]Lukás Kekely, Martin Spinler, Stepán Friedl, Jiri Sikora, Jan Korenek, Viktor Pus:
Demonstration of Full-Duplex Packet Transfers Over PCI Express with Sustained 200 Gbps Throughput. FPT 2018: 381-384 - [c22]Radek Isa, Pavel Benácek, Viktor Pus:
Verification of Generated RTL from P4 Source Code. ICNP 2018: 444-445 - 2017
- [c21]Pavel Benácek, Viktor Pus, Jan Korenek, Michal Kekely:
Line rate programmable packet processing in 100Gb networks. FPL 2017: 1 - 2016
- [j1]Lukas Kekely, Jan Kucera, Viktor Pus, Jan Korenek, Athanasios V. Vasilakos:
Software Defined Monitoring of Application Protocols. IEEE Trans. Computers 65(2): 615-626 (2016) - [c20]Zdenek Rosa, Tomás Cejka, Martin Zádník, Viktor Pus:
Building a feedback loop to capture evidence of network incidents. CNSM 2016: 292-296 - [c19]Pavel Benácek, Viktor Pus, Hana Kubátová:
P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers. FCCM 2016: 148-155 - [c18]Denis Matousek, Jan Korenek, Viktor Pus:
High-speed regular expression matching with pipelined automata. FPT 2016: 93-100 - 2015
- [c17]Petr Velan, Viktor Pus:
High-density network flow monitoring. IM 2015: 996-1001 - [c16]Viktor Pus, Petr Velan, Lukas Kekely, Jan Korenek, Pavel Minarík:
Hardware accelerated flow measurement of 100 Gb ethernet. IM 2015: 1147-1148 - 2014
- [c15]Tomás Závodník, Lukas Kekely, Viktor Pus:
CRC based hashing in FPGA using DSP blocks. DDECS 2014: 179-182 - [c14]Viktor Pus, Lukas Kekely, Jan Korenek:
Design methodology of configurable high performance packet parser for FPGA. DDECS 2014: 189-194 - [c13]Pavel Benácek, Hana Kubátová, Viktor Pus:
Architecture of Effective High-Speed Network Stream Merger. DSD 2014: 459-464 - [c12]Viktor Pus, Pavel Benácek:
Application specific processor with high level synthesized instructions (abstract only). FPGA 2014: 246 - [c11]Viktor Pus, Lukas Kekely, Tomás Závodník:
Using DSP blocks to compute CRC hash in FPGA (abstract only). FPGA 2014: 256 - [c10]Lukas Kekely, Viktor Pus, Pavel Benácek, Jan Korenek:
Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring. FPL 2014: 1-4 - [c9]Lukas Kekely, Viktor Pus, Jan Korenek:
Software Defined Monitoring of application protocols. INFOCOM 2014: 1725-1733 - 2012
- [b1]Viktor Pus:
Algoritmy klasifikace paketů ; Packet Classification Algorithms. Brno University of Technology, Czech Republic, 2012 - [c8]Viktor Pus:
Hardware Acceleration for Measurements in 100 Gb/s Networks. AIMS 2012: 46-49 - [c7]Viktor Pus, Lukas Kekely, Jan Korenek:
Low-latency modular packet header parser for FPGA. ANCS 2012: 77-78 - [c6]Viktor Pus, Jan Korenek:
Reducing memory in high-speed packet classification. IWCMC 2012: 437-442 - 2011
- [c5]Viktor Pus, Jiri Tobola, Vlastimil Kosar, Jan Kastil, Jan Korenek:
Netbench: Framework for Evaluation of Packet Processing Algorithms. ANCS 2011: 95-96 - [c4]Viktor Pus, Michal Kajan, Jan Korenek:
Hardware architecture for packet classification with prefix coloring. DDECS 2011: 231-236 - 2010
- [c3]Viktor Pus, Juraj Blaho, Jan Korenek:
Memory optimizations for packet classification algorithms in FPGA. DDECS 2010: 297-300
2000 – 2009
- 2009
- [c2]Juraj Blaho, Jan Korenek, Viktor Pus:
Memory optimization for packet classification algorithms. ANCS 2009: 165-166 - [c1]Viktor Pus, Jan Korenek:
Fast and scalable packet classification using perfect hash functions. FPGA 2009: 229-236
Coauthor Index
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