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Giulio Gambardella
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2020 – today
- 2023
- [j6]Timoteo García Bertoa
, Giulio Gambardella
, Nicholas J. Fraser
, Michaela Blott
, John McAllister
:
Fault-Tolerant Neural Network Accelerators With Selective TMR. IEEE Des. Test 40(2): 67-74 (2023) - [j5]Syed Asad Alam
, David Gregg
, Giulio Gambardella
, Thomas B. Preußer
, Michaela Blott
:
On the RTL Implementation of FINN Matrix Vector Unit. ACM Trans. Embed. Comput. Syst. 22(6): 94:1-94:27 (2023) - 2022
- [i12]Syed Asad Alam, David Gregg, Giulio Gambardella, Michael Preußer, Michaela Blott:
On the RTL Implementation of FINN Matrix Vector Compute Unit. CoRR abs/2201.11409 (2022) - 2021
- [j4]Michaela Blott
, Nicholas J. Fraser
, Giulio Gambardella
, Lisa Halder, Johannes Kath
, Zachary Neveu, Yaman Umuroglu
, Alina Vasilciuc, Miriam Leeser
, Linda Doyle
:
Evaluation of Optimized CNNs on Heterogeneous Accelerators Using a Novel Benchmarking Approach. IEEE Trans. Computers 70(10): 1654-1669 (2021) - 2020
- [c26]Michaela Blott, Johannes Kath, Lisa Halder, Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Miriam Leeser, Linda Doyle:
Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach. FPGA 2020: 317 - [c25]Ussama Zahid, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Kees A. Vissers:
FAT: Training Neural Networks for Reliable Inference Under Hardware Faults. ITC 2020: 1-10 - [i11]Ussama Zahid, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Kees A. Vissers:
FAT: Training Neural Networks for Reliable Inference Under Hardware Faults. CoRR abs/2011.05873 (2020)
2010 – 2019
- 2019
- [c24]Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf
, Kees A. Vissers:
Efficient Error-Tolerant Quantized Neural Network Accelerators. DFT 2019: 1-6 - [c23]Yifan Yang, Qijing Huang
, Bichen Wu, Tianjun Zhang, Liang Ma
, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer:
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. FPGA 2019: 23-32 - [i10]Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees A. Vissers:
Efficient Error-Tolerant Quantized Neural Network Accelerators. CoRR abs/1912.07394 (2019) - 2018
- [j3]Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser
, Kees A. Vissers:
FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 11(3): 16:1-16:23 (2018) - [c22]Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas
, Philip Heng Wai Leong
, Peter Y. K. Cheung:
Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic. ARC 2018: 29-42 - [c21]Thomas B. Preußer, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott:
Inference of quantized neural networks on heterogeneous all-programmable devices. DATE 2018: 833-838 - [c20]Vladimir Rybalkin, Alessandro Pappalardo, Muhammad Mohsin Ghaffar, Giulio Gambardella, Norbert Wehn
, Michaela Blott:
FINN-L: Library Extensions and Design Trade-Off Analysis for Variable Precision LSTM Networks on FPGAs. FPL 2018: 89-96 - [c19]Julian Faraone, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Philip H. W. Leong
, David Boland
:
Customizing Low-Precision Deep Neural Networks for FPGAs. FPL 2018: 97-100 - [i9]Thomas B. Preußer, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott:
Inference of Quantized Neural Networks on Heterogeneous All-Programmable Devices. CoRR abs/1806.08085 (2018) - [i8]Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser:
Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. CoRR abs/1807.03123 (2018) - [i7]Vladimir Rybalkin, Alessandro Pappalardo, Muhammad Mohsin Ghaffar, Giulio Gambardella, Norbert Wehn, Michaela Blott:
FINN-L: Library Extensions and Design Trade-off Analysis for Variable Precision LSTM Networks on FPGAs. CoRR abs/1807.04093 (2018) - [i6]Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung:
Accuracy to Throughput Trade-offs for Reduced Precision Neural Networks on Reconfigurable Logic. CoRR abs/1807.10577 (2018) - [i5]Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu:
FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks. CoRR abs/1809.04570 (2018) - [i4]Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer:
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. CoRR abs/1811.08634 (2018) - 2017
- [c18]Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers:
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. FPGA 2017: 65-74 - [c17]Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong
, Magnus Jahre
, Kees A. Vissers:
Scaling Binarized Neural Networks on Reconfigurable Logic. PARMA-DITAM@HiPEAC 2017: 25-30 - [c16]Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser
:
Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. ICCD 2017: 419-422 - [c15]Julian Faraone, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong
:
Compressing Low Precision Deep Neural Networks Using Sparsity-Induced Regularization in Ternary Networks. ICONIP (2) 2017: 393-404 - [i3]Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers:
Scaling Binarized Neural Networks on Reconfigurable Logic. CoRR abs/1701.03400 (2017) - [i2]Julian Faraone, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong:
Compressing Low Precision Deep Neural Networks Using Sparsity-Induced Regularization in Ternary Networks. CoRR abs/1709.06262 (2017) - 2016
- [i1]Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers:
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. CoRR abs/1612.07119 (2016) - 2015
- [j2]Stefano Di Carlo
, Giulio Gambardella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta:
SATTA: A Self-Adaptive Temperature-Based TDF Awareness Methodology for Dynamically Reconfigurable FPGAs. ACM Trans. Reconfigurable Technol. Syst. 8(1): 1:1-1:22 (2015) - [j1]Stefano Di Carlo
, Giulio Gambardella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta:
SA-FEMIP: A Self-Adaptive Features Extractor and Matcher IP-Core Based on Partially Reconfigurable FPGAs for Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2198-2208 (2015) - 2014
- [b1]Giulio Gambardella:
Dynamic partial reconfiguration for dependable systems. Polytechnic University of Turin, Italy, 2014 - [c14]Stefano Di Carlo
, Giulio Gambardella, Paolo Prinetto, Frank Reichenbach, Trond Løkstad, Gulzaib Rafiq:
On Enhancing Fault Injection's Capabilities and Performances for Safety Critical Systems. DSD 2014: 583-590 - [c13]Stefano Di Carlo
, Giulio Gambardella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta, Alessandro Vallero:
A novel methodology to increase fault tolerance in autonomous FPGA-based systems. IOLTS 2014: 87-92 - [c12]Teodora Sanislav, George Dan Mois, Silviu Folea, Liviu Miclea, Giulio Gambardella, Paolo Prinetto:
A cloud-based Cyber-Physical System for environmental monitoring. MECO 2014: 6-9 - 2013
- [c11]Stefano Di Carlo
, Giulio Gambardella, Marco Indaco, Ippazio Martella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta:
A software-based self test of CUDA Fermi GPUs. ETS 2013: 1-6 - [c10]Stefano Di Carlo
, Giulio Gambardella, Marco Indaco, Paolo Prinetto, Daniele Rolfo, Pascal Trotta:
Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS. FPL 2013: 1-4 - [c9]Stefano Di Carlo
, Giulio Gambardella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta, Piergiorgio Lanza:
FEMIP: A high performance FPGA-based features extractor & matcher for space applications. FPL 2013: 1-4 - [c8]Stefano Di Carlo
, Giulio Gambardella, Trong Huynh Bao
, Paolo Prinetto, Daniele Rolfo, Pascal Trotta:
ZipStream: Improving dependability in dynamic partial reconfiguration. IDT 2013: 1-6 - [c7]Stefano Di Carlo
, Giulio Gambardella, Piergiorgio Lanza, Paolo Prinetto, Daniele Rolfo, Pascal Trotta:
SAFE: A self adaptive frame enhancer FPGA-based IP-core for real-time space applications. IDT 2013: 1-6 - [c6]Stefano Di Carlo
, Giulio Gambardella, Marco Indaco, Ippazio Martella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta:
Increasing the robustness of CUDA Fermi GPU-based systems. IOLTS 2013: 234-235 - [c5]Stefano Di Carlo
, Giulio Gambardella, Ippazio Martella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta:
Fault mitigation strategies for CUDA GPUs. ITC 2013: 1-8 - 2011
- [c4]Stefano Di Carlo
, Giulio Gambardella, Marco Indaco, Daniele Rolfo, Paolo Prinetto:
MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches. Asian Test Symposium 2011: 401-406 - [c3]Stefano Di Carlo
, Giulio Gambardella, Marco Indaco, Daniele Rolfo, Paolo Prinetto:
A unifying formalism to support automated synthesis of SBSTs for embedded caches. EWDTS 2011: 39-42 - [c2]Stefano Di Carlo, Giulio Gambardella, Marco Indaco, Daniele Rolfo, Paolo Prinetto:
Validation & Verification of an EDA automated synthesis tool. IDT 2011: 48-52 - [c1]Stefano Di Carlo
, Giulio Gambardella, Marco Indaco, Daniele Rolfo, Gabriele Tiotto, Paolo Prinetto:
An area-efficient 2-D convolution implementation on FPGA for space applications. IDT 2011: 88-92
Coauthor Index
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