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Se-Hyeon Kang
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2000 – 2009
- 2007
- [c8]Se-Hyeon Kang, In-Cheol Park:
High Speed Sphere Decoding Based on Vertically Incremental Computation. ISCAS 2007: 665-668 - [c7]Se-Hyeon Kang, In-Cheol Park:
Fast and Area-Efficient Sphere Decoding Using Look-Ahead Search. VTC Spring 2007: 2384-2388 - 2006
- [j1]Se-Hyeon Kang, In-Cheol Park:
Loosely coupled memory-based decoding architecture for low density parity check codes. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(5): 1045-1056 (2006) - 2005
- [c6]Se-Hyeon Kang, In-Cheol Park:
Loosely coupled memory-based decoding architecture for low density parity check codes. CICC 2005: 703-706 - [c5]In-Cheol Park, Se-Hyeon Kang:
Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation. ISCAS (6) 2005: 5778-5781 - 2004
- [c4]Se-Hyeon Kang, In-Cheol Park:
Memory-based low density parity check code decoder architecture using loosely coupled two data-flows. ISCAS (2) 2004: 397-400 - 2003
- [c3]In-Cheol Park, Se-Hyeon Kang, Yongseok Yi:
Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation. ICCAD 2003: 138-141 - 2002
- [c2]Myoung-Cheol Shin, Seong-Il Park, Sung-Won Lee, Se-Hyeon Kang, In-Cheol Park:
Area-efficient digital baseband module for Bluetooth wireless communications. ISCAS (5) 2002: 729-732 - 2001
- [c1]Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park:
An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking. ICCD 2001: 511-512
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