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ORCIDFan Ye 0001
Ye Fan 0001
Person information
- affiliation: Fudan University, State-Key Laboratory of ASIC and Systems, Shanghai, China
Other persons with the same name
- Fan Ye (aka: Ye Fan) — disambiguation page
- Fan Ye 0002
![[0000-0002-8371-5436]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0002-8371-5436")
— Dalian University of Technology, Key Laboratory for Precision and Non-traditional Machining Technology, China - Fan Ye 0003 — Stony Brook University, Department of Electrical and Computer Engineering, NY, USA (and 2 more)
- Fan Ye 0004 — Morgan Stanley, New York, NY, USA (and 4 more)
- Fan Ye 0005 — University of York, UK
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2020 – today
- 2023
[j26]Xinwei Yu, Yan Wang, Fan Ye, Junyan Ren:
Low-Noise Low-Power Ultrasound AFE With Continuous TGC Built in Both TIA and Beamformer. IEEE Trans. Biomed. Circuits Syst. 17(5): 1062-1073 (2023)- [j25]Xinwei Yu, Zhi Chen, Siqing Wu, Lulu Liu, Hao Chi, Fan Ye, Junyan Ren:
28-nm CMOS Ultrasound AFE With Split Attenuation for Optimizing Gain-Range, Noise, and Area. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4742-4754 (2023) - [j24]Jingying Zhang, Sai-Weng Sin, Yan Liu, Fan Ye, Guoxing Wang, Maurits Ortmanns, Liang Qi:
On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 356-360 (2023) - [j23]Kaiquan Chen, Biao Wang, Yan Liu, Fan Ye, Sai-Weng Sin, Guoxing Wang, Yong Lian, Liang Qi:
A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 2724-2728 (2023) - [c115]Bingrong Lyu, Fan Ye, Junyan Ren:
A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm CMOS Technology. ASICON 2023: 1-4 - [c114]Siqing Wu, Xinwei Yu, Xingtao Zhu, Fan Ye, Junyan Ren:
A Three-stage Analog Low-Frequency Drift Calibration and DC Offset Correction Circuit for Ultrasonic AFE. ASICON 2023: 1-4 - [c113]Yutong Zhao, Yuguo Xiang, Fan Ye, Junyan Ren:
A 400-MS/s 12-bit Voltage-Time Hybrid ADC with a Ping-Pong SAR TDC for Speed Enhancement. ISCAS 2023: 1-5 - 2022
- [j22]Danfeng Zhai, Wenning Jiang, Xinru Jia, Jingchao Lan, Mingqiang Guo, Sai-Weng Sin, Fan Ye, Qi Liu, Junyan Ren, Chixiao Chen:
High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4944-4957 (2022) - [j21]Jingchao Lan, Yongzhen Chen, Xingchen Shen, Zhekan Ni, Yimin Wu, Fan Ye, Junyan Ren:
Effective Gain Analysis and Statistic Based Calibration for Ring Amplifier With Robustness to PVT Variation. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 304-308 (2022) - [c112]Xinwei Yu, Fan Ye, Junyan Ren:
A Low Noise TIA with Continuous Time-Gain Compensation for Ultrasound Transducers. APCCAS 2022: 1-4 - [c111]Yutong Zhao, Fan Ye, Junyan Ren:
A 500-MS/s 9-Bit Time-Domain ADC Using a Nonbinary Successive Approximation TDC. APCCAS 2022: 209-212 - [c110]Fan Ye, Heng Fang, Hao Zhou:
The Research of the Consistency Control Under the Condition of Time-Lag of Isomerism AUV Group Communication. BIC-TA 2022: 507-519 - [c109]Jingchao Lan, Danfeng Zhai, Yongzhen Chen, Zhekan Ni, Xingchen Shen, Fan Ye, Junyan Ren:
A 2.5-GS/s Time-Interleaved SAR-Assisted Ringamp-Based Pipelined ADC with Digital Background Calibration. ISCAS 2022: 2655-2659 - [c108]Jingchao Lan, Yuxuan Zhang, Fan Ye, Junyan Ren:
A Single-Channel 1.25-GS/s 11-bit Pipelined ADC with Robust Floating-Powered Ring Amplifier and First-Order Gain Error Calibration. MWSCAS 2022: 1-5 - [c107]Lulu Liu, Yimin Wu, Xinwei Yu, Fan Ye, Junyan Ren:
A Branch-Gain-Balanced LNA Based on Voltage- Controlled Resistor Feedback and Shared CMFB Amplifier. MWSCAS 2022: 1-4 - [c106]Wenhan Lu, Yimin Wu, Fan Ye, Junyan Ren:
A Broadband LMS-based Band-split Crosstalk Cancellation Method for Ultrasound Systems. MWSCAS 2022: 1-4 - 2021
- [j20]Manxin Li, Yuting Yao, Biao Hu, Jipeng Wei, Yong Chen, Shunli Ma, Fan Ye, Junyan Ren:
A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS. IEEE Access 9: 77545-77554 (2021) - [j19]Yan Zheng, Jingchao Lan, Fan Ye, Junyan Ren:
A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET. IEEE Access 9: 169107-169121 (2021) - [j18]Yuefeng Cao, Shumin Zhang, Tianli Zhang, Yongzhen Chen, Yutong Zhao, Chixiao Chen, Fan Ye, Junyan Ren:
A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 641-654 (2021) - [c105]Hao Chi, Jun Xu, Fan Ye, Junyan Ren:
A High Linearity and Low Noise Anti-Aliasing Filter for ADCs. ASICON 2021: 1-4 - [c104]Ziwei Li, Yutong Zhao, Guoyao Wu, Fan Ye, Junyan Ren:
A Wide-Range 12b 150MS/s P-SAR ADC with Open-Loop Residue Amplifier for Ultrasound AFE. ASICON 2021: 1-4 - [c103]Liang Qi, Xinyu Qin, Sai-Weng Sin, Chixiao Chen, Fan Ye, Guoyong Shi, Guoxing Wang:
Advances in Continuous-time MASH ΔΣ Modulators. ASICON 2021: 1-4 - [c102]Jingqi Wang, Fan Ye, Junyan Ren:
A Three-Stage Comparator with High Speed and Low Power. ASICON 2021: 1-4 - [c101]Guoyao Wu, Ziwei Li, Yutong Zhao, Fan Ye, Junyan Ren:
A 5-bit High-Linearity, Binary-Recombination-Redundancy Sub-SAR ADC in 300MS/s, 14-bit Pipelined-SAR ADC. ASICON 2021: 1-4 - [c100]Yan Zheng, Jingchao Lan, Fan Ye, Junyan Ren:
A 68.36 dB 12 bit 100MS/s SAR ADC with a low-noise comparator in 14-nm CMOS FinFet. ASICON 2021: 1-4 - [c99]Min Chen, Yutong Zhao, Nuo Xu, Fan Ye, Junyan Ren:
A Partially Binarized and Fixed Neural Network Based Calibrator for SAR-Pipelined ADCs Achieving 95.0-dB SFDR. ISCAS 2021: 1-4 - [c98]Wenbin He, Fan Ye, Junyan Ren:
An 11-Bit 500 MS/s Two-Step SAR ADC with Non-Attenuated Passive Residue Transfer. ISCAS 2021: 1-4 - [c97]Jingying Zhang, Yang Zhao, Mingyi Chen, Chixiao Chen, Fan Ye, Liang Qi:
Self-coupled MASH Delta-Sigma Modulator with Zero Optimization. ISOCC 2021: 1-2 - [c96]Ziwei Li, Guoyao Wu, Yutong Zhao, Fan Ye, Junyan Ren:
Resistive Degeneration Linearization Dynamic Residue Amplifiers for Pipelined ADCs. ISOCC 2021: 9-10 - [c95]Jingchao Lan, Yan Zheng, Yimin Wu, Min Chen, Fan Ye, Junyan Ren:
A High Linearity Bootstrapped Switch with Leakage Current Suppressed for GS/s Sampling Rate ADC. ISOCC 2021: 129-130 - [c94]Danfeng Zhai, Chixiao Chen, Liang Qi, Fan Ye, Junyan Ren:
Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration. ISOCC 2021: 246-247 - [c93]Min Chen, Nuo Xu, Yutong Zhao, Fan Ye, Junyan Ren:
A Hardware-Efficient Calibrator for SAR-Pipelined ADCs with a Layer-based Sharing Neural Network. MWSCAS 2021: 125-128 - [c92]Danfeng Zhai, Peizhe Li, Jiushan Zhang, Chixiao Chen, Fan Ye, Junyan Ren:
Additive Neural Network Based Static and Dynamic Distortion Modeling for Prior-Knowledge-Free Nyquist ADC Characterization. MWSCAS 2021: 292-296 - [c91]Jingchao Lan, Yan Zheng, Yimin Wu, Fan Ye, Junyan Ren:
A Novel Ring Amplifier with Low Common-Mode Voltage Variation and Noise Reduction Using Floating Power Technique. MWSCAS 2021: 949-953 - 2020
- [c90]Yimin Wu, Jingchao Lan, Min Chen, Fan Ye, Junyan Ren:
A 16-channel 50MS/s 14bit Pipelined-SAR ADC for Integrated Ultrasound Imaging Systems. APCCAS 2020: 3-6 - [c89]Yimin Wu, Shuai Li, Longheng Luo, Fan Ye, Junyan Ren:
An Area-Power-Efficient AFE with NS-SAR ADC For High-Frequency Ultrasound Applications. APCCAS 2020: 7-10 - [c88]Ziwei Li, Wenbin He, Fan Ye, Junyan Ren:
A Low-Power Low-Noise Dynamic Comparator With Latch-Embedding Floating Amplifier. APCCAS 2020: 39-42 - [c87]Wenbin He, Ziwei Li, Fan Ye, Junyan Ren:
A Low Power Reference Voltage Buffer and High Density Unit capacitor in a 12b 200MS/s SAR ADC. APCCAS 2020: 82-85 - [c86]Min Chen, Yimin Wu, Jingchao Lan, Fan Ye, Chixiao Chen, Junyan Ren:
A Calibration Scheme for Nonlinearity of the SAR-Pipelined ADCs Based on a Shared Neural Network. APCCAS 2020: 205-208 - [c85]Yan Zheng, Fan Ye, Junyan Ren:
A 13 Bit 100 MS/s SAR ADC with 74.57 dB SNDR in 14-nm CMOS FinFET. ISCAS 2020: 1-4 - [c84]Wenbin He, Fan Ye, Junyan Ren:
A Fast Response Reference Voltage Buffer for 12b 200MS/s SAR ADC. MWSCAS 2020: 337-340 - [c83]Fan Ye, Junyan Ren:
A 12-bit SAR ADC Using Pseudo-Dynamic Weighting C-DAC for Capacitor Error Calibration. MWSCAS 2020: 746-749
2010 – 2019
- 2019
- [j17]Zhekan Ni, Yongzhen Chen, Fan Ye, Junyan Ren:
A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic. Microelectron. J. 84: 59-66 (2019) - [c82]Longheng Luo, Xingchen Shen, Jianguo Diao, Fan Ye, Junyan Ren:
A Comparator-Reused Dynamic-Amplifier for Noise-Shaping SAR ADC. ASICON 2019: 1-4 - [c81]Yuting Yao, Jipeng Wei, Manxin Li, Shunli Ma, Fan Ye, Junyan Ren:
A 256MHz Analog Baseband Chain with tunable Bandwidth and Gain for UWB Receivers. ASICON 2019: 1-4 - [c80]Shumin Zhang, Yuefeng Cao, Fan Ye, Junyan Ren:
A 10b 250MS/s SAR ADC with Speed-Enhanced SAR Logic and Free Time More Than a Half of Sampling Period. ASICON 2019: 1-4 - [c79]Wenbin He, Fan Ye, Junyan Ren:
A 40Gb/s Low Power Transmitter with 2-tap FFE and 40: 1 MUX in 28nm CMOS Technology. ASICON 2019: 594-597 - [c78]Tianli Zhang, Yuefeng Cao, Shumin Zhang, Chixiao Chen, Fan Ye, Junyan Ren:
Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR. ESSCIRC 2019: 189-192 - [c77]Yongzhen Chen, Xingchen Shen, Zhekan Ni, Jingchao Lan, Chixiao Chen, Fan Ye, Junyan Ren:
A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps. ESSCIRC 2019: 197-200 - [c76]Fan Ye, Shuai Li, Min Zhu, Zhekan Ni, Junyan Ren:
A 13-bit 180-MS/s SAR ADC with Efficient Capacitor-Mismatch Estimation and Dither Enhancement. ISCAS 2019: 1-4 - [c75]Hang Hu, Calvin Y. Lee, Ahmed ElShater, Zhiyuan Dai, Fan Ye, Un-Ku Moon:
Simultaneous STF and NTF Estimation in CTΔΣ Modulators with ARMA-Model. ISCAS 2019: 1-5 - [c74]Longheng Luo, Yimin Wu, Jipeng Wei, Fan Ye, Junyan Ren:
A Capacitively-Degenerated High-Linearity Dynamic Amplifier using a Real-Time Gain Detection Technique. ISCAS 2019: 1-4 - [c73]Jipeng Wei, Yuting Yao, Longheng Luo, Shunli Ma, Fan Ye, Junyan Ren:
A Novel Nauta Transconductor for Ultra-Wideband gm-C Filter with Temperature Calibration. ISCAS 2019: 1-4 - [c72]Shuai Li, Jianguo Diao, Yimin Wu, Fan Ye, Junyan Ren:
A 20MHz Bandwidth Band-Pass Noise-Shaping SAR ADC With OPAMP Sharing Switched-Capacitor Filter. MWSCAS 2019: 109-112 - [c71]Yimin Wu, Jingchao Lan, Shuai Li, Fan Ye, Junyan Ren:
A Ring Amplifier Based Current Feedback Continuous Time PGA for High Frequency Ultrasound Applications. MWSCAS 2019: 141-144 - [c70]Longheng Luo, Shuai Li, Jipeng Wei, Yimin Wu, Fan Ye, Junyan Ren:
A Band-Pass Noise-Shaping Modulator Using the Error-Feedback Structure on a 10-bit SAR ADC. MWSCAS 2019: 766-769 - [c69]Jianguo Diao, Shuai Li, Yimin Wu, Fan Ye, Jun Xu, Junyan Ren:
Energy-Efficient Analog Frond-End Design for Ultrasound Imaging Applications. MWSCAS 2019: 1171-1174 - 2018
- [j16]Yongzhen Chen, Fan Ye, Junyan Ren:
An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration. Microelectron. J. 73: 52-58 (2018) - [j15]Yongzhen Chen, Jingjing Wang, Hang Hu, Fan Ye, Junyan Ren:
A Time-Interleaved SAR Assisted Pipeline ADC With a Bias-Enhanced Ring Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1584-1588 (2018) - [c68]Yuefeng Cao, Yongzhen Chen, Zhekan Ni, Fan Ye, Junyan Ren:
An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC. APCCAS 2018: 18-21 - [c67]Zhekan Ni, Yongzhen Chen, Fan Ye, Junyan Ren:
A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic. APCCAS 2018: 42-45 - [c66]Yuefeng Cao, Tianli Zhang, Yongzhen Chen, Fan Ye, Junyan Ren:
An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs. ISCAS 2018: 1-5 - [c65]Yongzhen Chen, Zhekan Ni, Yuefeng Cao, Fan Ye, Junyan Ren:
A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation. ISCAS 2018: 1-4 - [c64]Manxin Li, Yongzhen Chen, Fan Ye, Junyan Ren:
A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC. ISCAS 2018: 1-4 - [c63]Tianli Zhang, Yuefeng Cao, Fan Ye, Junyan Ren:
Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC. ISCAS 2018: 1-5 - [c62]Zhiyuan Dai, Hang Hu, Yimin Wu, Fan Ye, Junyan Ren:
A Third-order Band-pass Fully-passive Noise-Shaping Modulator Based on a Time-interleaved SAR ADC. MWSCAS 2018: 101-104 - [c61]Longheng Luo, Yimin Wu, Jianguo Diao, Fan Ye, Junyan Ren:
Low Power Low Noise Amplifier with DC Offset Correction at 1 V Supply Voltage for Ultrasound Imaging Systems. MWSCAS 2018: 137-140 - [c60]Zhiyuan Dai, Hang Hu, Yongzhen Chen, Fan Ye, Junyan Ren:
A 12-Bit ENOB 8MHz BW Noise-Shaping SAR ADC Using High-Speed Switches. MWSCAS 2018: 392-395 - 2017
- [j14]Dezhi Xing, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, Rui Paulo Martins:
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1168-1172 (2017) - [c59]Zhiyuan Dai, Hang Hu, Manxin Li, Fan Ye, Junyan Ren:
A 0.87 mW 7MHz-BW 76dB-SNDR passive noise-shaping modulator based on a SAR ADC. ASICON 2017: 28-31 - [c58]Xiaoqing Chen, Fan Ye, Junyan Ren:
A 13-bit non-binary weighted SAR ADC with bridge structure using digital calibration for capacitor weight error. ASICON 2017: 32-35 - [c57]Hang Hu, Zhiyuan Dai, Manxin Li, Fan Ye, Junyan Ren:
A 320MS/s 7-b flash-SAR ADC with preamplifier sharing technique. ASICON 2017: 179-182 - [c56]Yimin Wu, Yongzhen Chen, Manxin Li, Fan Ye, Junyan Ren:
A stacked-packaged 16-channel ADC for ultrasound application. ASICON 2017: 245-248 - [c55]Yongzhen Chen, Yimin Wu, Fubiao Cao, Fan Ye, Junyan Ren:
A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs. ASICON 2017: 295-298 - [c54]Hang Hu, Manxin Li, Zhiyuan Dai, Fan Ye, Junyan Ren:
A 15MHz BW continuous-time ΔΣ modulator with high speed digital ELD compensation. ASICON 2017: 686-689 - [c53]Fubiao Cao, Yongzhen Chen, Zhiyuan Dai, Fan Ye, Junyan Ren:
An input buffer for 12bit 2GS/s ADC. ASICON 2017: 750-753 - [c52]Fubiao Cao, Yongzhen Chen, Yuefeng Cao, Fan Ye, Junyan Ren:
A proved dither-injection method for memory effect in double sampling pipelined ADC. ASICON 2017: 754-757 - [c51]Manxin Li, Hang Hu, Zhiyuan Dai, Fan Ye, Junyan Ren:
A 12bit asynchronous SAR-incremental sub-range ADC. ASICON 2017: 835-838 - [c50]Fan Ye, Zuobin Ying, Yiwen Zhang, Cheng Zheng:
Smartly Searching Multimedia Data in Heterogeneous Mobile Ad Hoc Networks. FSDM 2017: 275-284 - [c49]Yongzhen Chen, Jingjing Wang, Hang Hu, Fan Ye, Junyan Ren:
A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier. ISCAS 2017: 1-4 - [c48]Yuefeng Cao, Yongzhen Chen, Tianli Zhang, Fan Ye, Junyan Ren:
An improved ring amplifier with process- and supply voltage-insensitive dead-zone. MWSCAS 2017: 811-814 - [c47]Hang Hu, Zemin Feng, Chixiao Chen, Fan Ye, Junyan Ren:
High speed digital ELD compensation with hybrid thermometer coding in CT ΔΣ modulators. MWSCAS 2017: 1009-1012 - 2016
- [j13]Jianguo Yang, Xiaoyong Xue, Juan Xu, Fan Ye, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu:
A self-adaptive write driver with fast termination of step-up pulse for ReRAM. IEICE Electron. Express 13(7): 20160195 (2016) - 2015
- [j12]Chixiao Chen, Jixuan Xiang, Jiang Fan, Xu Jun, Ye Fan, Junyan Ren:
A 270-MS/s 6-b SAR ADC with preamplifier sharing and self-locking comparators. IEICE Electron. Express 12(5): 20141143 (2015) - [j11]Weiru Gu, Fan Ye, Junyan Ren:
Switch-back based on charge equalization switching technique for SAR ADC. IEICE Electron. Express 12(6): 20150036 (2015) - [j10]Yuan Su, Fan Ye, Junyan Ren:
A high power-efficient LVDS output driver with adjustable feed-forward capacitor compensation. IEICE Electron. Express 12(11): 20150368 (2015) - [j9]Chixiao Chen, Zemin Feng, Jun Xu, Fan Ye, Junyan Ren:
An ARMA-Model-Based NTF Estimation on Continuous-Time ΔΣ Modulators. IEEE Trans. Circuits Syst. II Express Briefs 62-II(8): 721-725 (2015) - [c46]Fazhi An, Shunli Ma, Qian Chen, Guangyao Zhou, Fan Ye, Junyan Ren:
A wide-division-ratio 100MHz-to-5GHz multi-modulus divider chain for wide-band PLL. ASICON 2015: 1-4 - [c45]Qian Chen, Fazhi An, Guangyao Zhou, Shunli Ma, Fan Ye, Junyan Ren:
A 39 GHz-80 GHz millimeter-wave frequency doubler with low power consumption in 65nm CMOS tehnology. ASICON 2015: 1-4 - [c44]Yuan Su, Yimin Wu, Qiang Zhang, Xuerong Zhou, Fan Ye, Junyan Ren:
LVDS transmitter with optimized high power-efficiency 8: 1 MUX. ASICON 2015: 1-4 - [c43]Jingjing Wang, Rongjin Xu, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren:
100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array. ASICON 2015: 1-4 - [c42]Weizhen Wang, Hao Zhou, Fan Ye, Junyan Ren:
An 8-bit 4fs-step digitally controlled delay element with two cascaded delay units. ASICON 2015: 1-4 - [c41]Rongjin Xu, Yongzhen Chen, Mingshuo Wang, Ning Li, Fan Ye, Junyan Ren:
A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network. ASICON 2015: 1-4 - [c40]Xiangyan Xue, Xuerong Zhou, Fan Ye, Junyan Ren:
A 100MS/s 5bit fully digital flash ADC with standard cells. ASICON 2015: 1-4 - [c39]Xuerong Zhou, Xiangyan Xue, Fan Ye, Junyan Ren:
I/Q imbalance estimation in OFDM systems. ASICON 2015: 1-4 - [c38]Guangyao Zhou, Shunli Ma, Fazhi An, Ning Li, Fan Ye, Junyan Ren:
A 30-GHz to 39-GHz mm-Wave low-power injection-locked frequency divider in 65nm CMOS. ASICON 2015: 1-4 - [c37]Shunli Ma, Guangyao Zhou, Jianbing Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren:
A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system. ESSCIRC 2015: 136-139 - 2014
- [j8]Mingshuo Wang, Fan Ye, Wei Li, Junyan Ren:
A 42fJ 8-bit 1.0-GS/s folding and interpolating ADC with 1GHz signal bandwidth. IEICE Electron. Express 11(2): 20130986 (2014) - [j7]Mingshuo Wang, Li Lin, Fan Ye, Junyan Ren:
A 7 bit 1 GS/s pipelined folding and interpolating ADC with coarse-stage-free joint encoding. IEICE Electron. Express 11(12): 20140371 (2014) - [c36]Yuankun Xue, Zhiliang Qian, Paul Bogdan, Fan Ye, Chi-Ying Tsui:
Disease Diagnosis-on-a-Chip: Large Scale Networks-on-Chip based Multicore Platform for Protein Folding Analysis. DAC 2014: 104:1-104:6 - [c35]Chixiao Chen, Zemin Feng, Huabin Chen, Mingshuo Wang, Jun Xu, Fan Ye, Junyan Ren:
A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier. ISCAS 2014: 2361-2364 - [c34]Guoxian Dai, Chixiao Chen, Shunli Ma, Fan Ye, Junyan Ren:
A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators. ISCAS 2014: 2365-2368 - 2013
- [j6]Bei Yu, Chixiao Chen, Fan Ye, Junyan Ren:
A mixed sample-time error calibration technique in time-interleaved ADCs. IEICE Electron. Express 10(24): 20130882 (2013) - [j5]Zhenyu Wang, Mingshuo Wang, Weiru Gu, Chixiao Chen, Fan Ye, Junyan Ren:
A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(11): 2834-2844 (2013) - [j4]Liang Liu, Junyan Ren, Jun Zhou, Fan Ye:
Carrier Frequency Offset and I/Q Imbalance Compensation for MB-OFDM Based UWB System. Wirel. Pers. Commun. 71(2): 1095-1107 (2013) - [c33]Yongzhen Chen, Chixiao Chen, Qiang Zhang, Fan Ye, Junyan Ren:
A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique. ASICON 2013: 1-4 - [c32]Zemin Feng, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren:
A finite gain bandwidth compensation method for low power continuous-time ΣΔ modulator. ASICON 2013: 1-4 - [c31]Jiasen Huang, Hao Chen, Junyan Ren, Fan Ye:
A novel joint estimation and compensation algorithm for non-idealities of analog front-end in DC-OFDM system. ASICON 2013: 1-4 - [c30]Bing Jing, Hao Chen, Fan Ye, Ning Li, Junyan Ren:
Low-complexity synchronizer used in DC-OFDM UWB system. ASICON 2013: 1-4 - [c29]Bing Jing, Yuankun Xue, Fan Ye, Ning Li, Junyan Ren:
Automatic gain control algorithm with high-speed and double closed-loop in UWB system. ASICON 2013: 1-4 - [c28]Jian Mei, Jixuan Xiang, Huabin Chen, Fan Ye, Junyan Ren:
A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC. ASICON 2013: 1-4 - [c27]Yuwen Wang, Fan Ye, Junyan Ren:
A DLL based low-phase-noise clock multiplier with offset-tolerant PFD. ASICON 2013: 1-4 - [c26]Jixuan Xiang, Jian Mei, Hao Chang, Fan Ye:
A 7.9-fJ/conversion-step 8-b 400-MS/s 2-b-per-cycle SAR ADC with A preset capacitive DAC. ASICON 2013: 1-4 - [c25]Weiru Gu, Hao Zhou, Tao Lin, Zhenyu Wang, Fan Ye, Junyan Ren:
Power efficient SAR ADC with optimized settling technique. MWSCAS 2013: 1156-1159 - 2012
- [j3]Xiaolong Wang, Fan Ye, Junyan Ren:
Comments on "Estimation of Carrier Frequency Offset With I/Q Mismatch Using Pseudo-Offset Injection in OFDM Systems". IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(11): 2795-2798 (2012) - [c24]Yiwen Zhang, Xiaoshi Zhu, Chixiao Chen, Fan Ye, Junyan Ren:
A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation. APCCAS 2012: 128-131 - [c23]Long Cheng, Yu-Jing Lin, Fan Ye, Ning Li, Junyan Ren:
Output-dependent delay cancellation technique for high-accuracy current-steering DACs. ISCAS 2012: 2729-2732 - [c22]Mingshuo Wang, Tao Lin, Fan Ye, Ning Li, Junyan Ren:
A 1.2 V 1.0-GS/s 8-bit Voltage-Buffer-Free Folding and interpolating ADC. MWSCAS 2012: 274-277 - [c21]Long Cheng, Chixiao Chen, Fan Ye, Ning Li, Junyan Ren:
A digitally calibrated current-steering DAC with current-splitting array. MWSCAS 2012: 278-281 - [c20]Xiaolong Wang, Yuankun Xue, Liang Liu, Fan Ye, Junyan Ren:
Carrier Frequency Offset estimation in the Presence of I/Q Mismatch for Wideband OFDM systems. MWSCAS 2012: 924-927 - [c19]Chixiao Chen, ShengChang Cai, Jialiang Xu, Xiaoshi Zhu, Fan Ye, Junyan Ren:
An 8-bit 100-MS/s Digital-to-Skew Converter with 200-ps range for time-interleaved sampling. MWSCAS 2012: 1100-1103 - [c18]Long Cheng, Yu-Jing Lin, Mingshuo Wang, Fan Ye, Ning Li, Junyan Ren:
A cancellation technique for output-dependent delay differences in high-accuracy DACs. MWSCAS 2012: 1104-1107 - 2011
- [j2]Liang Liu, Junyan Ren, Xiaojing Ma, Fan Ye:
A Parallel Early-Pruned K-Best MIMO Signal Detector Up to 1.9Gb/s. Wirel. Pers. Commun. 57(4): 695-705 (2011) - [c17]Peng Zhang, Fan Ye, Junyan Ren:
Class-AB CMOS buffer with floating class-AB control. ASICON 2011: 120-123 - [c16]Qianqian Ha, Fan Ye, Chixiao Chen, Xiaoshi Zhu, Mingshuo Wang, Yu-Jing Lin, Ning Li, Junyan Ren:
A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application. ASICON 2011: 492-495 - [c15]Yuan Yao, Fan Ye, Junyan Ren:
Area efficient LDPC decoder design for parallel layered decoding. ASICON 2011: 679-682 - [c14]Chen Shu, Guanghua Shu, Jun Xu, Fan Ye, Junyan Ren:
A 12-bit 50-MSPS SHA-less opamp-sharing Analog-to-Digital converter in 65nm CMOS. ASICON 2011: 894-897 - [c13]Bei Yu, Chixiao Chen, Yu Zhu, Peng Zhang, Yiwen Zhang, Xiaoshi Zhu, Fan Ye, Junyan Ren:
A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation. A-SSCC 2011: 349-352 - [c12]Long Cheng, Fan Ye, Hai-Feng Yang, Ning Li, Jun Xu, Junyan Ren:
Nyquist-rate time-interleaved current-steering DAC with dynamic channel matching. ISCAS 2011: 5-8 - 2010
- [j1]Liang Liu, Fan Ye, Xiaojing Ma, Tong Zhang, Junyan Ren:
A 1.1-Gb/s 115-pJ/bit Configurable MIMO Detector Using 0.13- muhboxm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 57-II(9): 701-705 (2010) - [c11]Jun Zhou, Liang Liu, Fan Ye, Junyan Ren:
Joint estimation and compensation for front-end imperfection in MB-OFDM UWB systems. ISCAS 2010: 2135-2138 - [c10]Danfeng Chen, Haipeng Fu, Yunfeng Chen, Wei Li, Fan Ye, Ning Li, Junyan Ren:
A sideband-suppressed low-power synthesizer for 14-band dual-carrier MB-OFDM UWB transceivers. ISCAS 2010: 2139-2192 - [c9]Guanghua Shu, Fan Ye, Yao Guo, Mingjun Fan, Junyan Ren, Jun Xu, Ning Li, Cheng Chen:
A 0.22 pJ/step subsampling ADC with fast input-tracking sampling and simplified opamp sharing. ISCAS 2010: 3016-3019
2000 – 2009
- 2009
- [c8]Lei Luo, Kaihui Lin, Long Cheng, Liren Zhou, Fan Ye, Junyan Ren:
A digitally calibrated 14-bit linear 100-MS/s pipelined ADC with wideband sampling frontend. ESSCIRC 2009: 472-475 - [c7]Mingjun Fan, Junyan Ren, Yao Guo, Yuanwen Li, Fan Ye, Ning Li:
A Novel Operational Amplifier for Low-voltage Low-power SC Circuits. ISCAS 2009: 2289-2292 - [c6]Ping Lu, Danfeng Chen, Fan Ye, Junyan Ren:
A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator. SoCC 2009: 39-42 - 2008
- [c5]Liang Liu, Xiaojing Ma, Fan Ye, Junyan Ren:
Design of Highly-Parallel, 2.2Gbps Throughput Signal Detector for MIMO Systems. ICC 2008: 742-745 - 2007
- [c4]Zhuo Xu, Junyan Ren, Xuejing Wang, Fan Ye:
Implementation of Folded Sliding Block Viterbi Decoders for MB-OFDM UWB Communication System. ISCAS 2007: 2574-2577 - [c3]Liang Liu, Junyan Ren, Xuejing Wang, Fan Ye:
Design of Low-Power, 1GS/s Throughput FFT Processor for MIMO-OFDM UWB Communication System. ISCAS 2007: 2594-2597 - [c2]Xuejing Wang, Liang Liu, Fan Ye, Junyan Ren, Bo Hu:
A Novel Synchronizer for OFDM-based UWB System on New Preamble Design. PIMRC 2007: 1-5 - 2006
- [c1]Lu Ping, Ye Fan, Junyan Ren:
A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet. ISCAS 2006
Coauthor Index
[j26] [j25] [c115] [c114] [c113] [j22] [j21] [c112] [c111] [c109] [c108] [c107] [c106] [j20] [j19] [j18] [c105] [c104] [c102] [c101] [c100] [c99] [c98] [c96] [c95] [c94] [c93] [c92] [c91] [c90] [c89] [c88] [c87] [c86] [c85] [c84] [c83] [j17] [c82] [c81] [c80] [c79] [c78] [c77] [c76] [c74] [c73] [c72] [c71] [c70] [c69] [j16] [j15] [c68] [c67] [c66] [c65] [c64] [c63] [c62] [c61] [c60] [j14] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [c49] [c48] [c47] [j12] [j11] [j10] [j9] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [j8] [j7] [c35] [c34] [j6] [j5] [j4] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c25] [j3] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [j2] [c17] [c16] [c15] [c14] [c13] [c12] [j1] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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