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2020 – today
- 2022
[c5]Bahram Zand, Mike Bichan, Alireza Mahmoodi, Mansour Shashaani, Jing Wang, Ruslana Shulyzki, James Guthrie, Katya Tyshchenko, Junhong Zhao, Eric Liu, Nima Soltani, Al Freeman, Rishi Anand, Syed Rubab, Ranjit Khela, Shaham Sharifian, Karl Herterich:
A 1-58.125Gb/s, 5-33dB IL Multi-Protocol Ethernet-Compliant Analog PAM-4 Receiver with 16 DFE Taps in 10nm. ISSCC 2022: 1-3- 2020
- [c4]Mike Bichan, Clifford Ting, Bahram Zand, Jing Wang, Ruslana Shulyzki, James Guthrie, Katya Tyshchenko, Junhong Zhao, Alireza Parsafar, Eric Liu, Aynaz Vatankhahghadim, Shaham Sharifian, Aleksey Tyshchenko, Michael De Vita, Syed Rubab, Sitaraman Iyer, Fulvio Spagna, Noam Dolev:
A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol. CICC 2020: 1-4
2010 – 2019
- 2014
- [c3]Mike Bichan, Dustin Dunwell, Qiwei Wang, Anthony Chan Carusone
:
A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC. ISCAS 2014: 1320-1323
2000 – 2009
- 2008
- [c2]Mike Bichan, Anthony Chan Carusone:
A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacing. CICC 2008: 611-614 - 2007
- [c1]Mike Bichan, Anthony Chan Carusone:
Crosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip Links. ISCAS 2007: 189-192
Coauthor Index
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