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ORCIDPablo Viana
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2010 – 2019
- 2014
[c8]Mohamad Hammam Alsafrjalani, Ann Gordon-Ross, Pablo Viana:
Minimum Effort Design Space Subsetting for Configurable Caches. EUC 2014: 65-72
2000 – 2009
- 2008
- [c7]Pablo Viana, Ann Gordon-Ross, Edna Barros
, Frank Vahid:
A table-based method for single-pass cache optimization. ACM Great Lakes Symposium on VLSI 2008: 71-76 - 2007
- [c6]Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros:
A one-shot configurable-cache tuner for improved energy and performance. DATE 2007: 755-760 - [c5]André Silva, Guilherme Álvaro R. M. Esmeraldo, Edna Barros, Pablo Viana:
Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass. IEEE International Workshop on Rapid System Prototyping 2007: 3-9 - 2006
- [c4]Pablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid:
Configurable cache subsetting for fast cache tuning. DAC 2006: 695-700 - [c3]Abel Guilhermino Silva-Filho, Pablo Viana, Edna Barros, Manoel Eusébio de Lima:
Tuning Mechanism for Two-Level Cache Hierarchy Intended for Instruction Caches and Low Energy Consumption. SBAC-PAD 2006: 125-132 - 2004
- [c2]Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo:
Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology. DATE 2004: 734-735 - 2003
- [c1]Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo:
Exploring Memory Hierarchy with ArchC. SBAC-PAD 2003: 2-9
Coauthor Index
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