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ORCIDAkira Tanabe
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2010 – 2019
- 2015
[c5]Yasuo Hayashibara, Hideaki Minakata, Kiyoshi Irie, Daiki Maekawa, George Tsukioka, Yasufumi Suzuki, Taiitiro Mashiko, Yusuke Ito, Ryu Yamamoto, Masayuki Ando, Shouta Hirama, Yukari Suzuki, Chisato Kasebayashi, Akira Tanabe, Youta Seki, Moeno Masuda, Yuya Hirata, Yuuki Kanno, Tomotaka Suzuki, Joshua Supratman, Kosuke Machi, Shigechika Miki, Yoshitaka Nishizaki, Kenji Kanemasu, Hajime Sakamoto:
CIT Brains KidSize Robot: RoboCup 2015 KidSize League Winner. RoboCup 2015: 153-164- [c4]Makoto Ueki, K. Takeuchi, T. Yamamoto, Akira Tanabe, N. Ikarashi, M. Saitoh, T. Nagumo, Hiroshi Sunamura, Mitsuru Narihiro, Kazuya Uejima, Koji Masuzaki, Naoya Furutake, S. Saito, Y. Yabe, Akira Mitsuiki, Koichi Takeda, Takashi Hase, Yoshihiro Hayashi:
Low-power embedded ReRAM technology for IoT applications. VLSIC 2015: 108- - 2011
- [j6]Akira Tanabe, Ken'ichiro Hijioka, Hirokazu Nagase, Yoshihiro Hayashi
:
A Novel Variable Inductor Using a Bridge Circuit and Its Application to a 5-20 GHz Tunable LC-VCO. IEEE J. Solid State Circuits 46(4): 883-893 (2011)
2000 – 2009
- 2009
- [j5]Shunichi Kaeriyama, Yasushi Amamiya, Hidemi Noguchi, Zin Yamazaki, Tomoyuki Yamase, Ken'ichi Hosoya, Minoru Okamoto, Shiro Tomari, Hiroshi Yamaguchi, Hiroaki Shoda, Hironobu Ikeda, Shinji Tanaka, Tsugio Takahashi, Risato Ohhira, Arihide Noda, Ken'ichiro Hijioka, Akira Tanabe, Sadao Fujita, Nobuhiro Kawahara:
A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems. IEEE J. Solid State Circuits 44(12): 3568-3579 (2009) - [c3]Yasushi Amamiya, Shunichi Kaeriyama, Hidemi Noguchi, Zin Yamazaki, Tomoyuki Yamase, Ken'ichi Hosoya, Minoru Okamoto, Shiro Tomari, Hiroshi Yamaguchi, Hiroaki Shoda, Hironobu Ikeda, Shinji Tanaka, Tsugio Takahashi, Risato Ohhira, Arihide Noda, Ken'ichiro Hijioka, Akira Tanabe, Sadao Fujita, Nobuhiro Kawahara:
A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems. ISSCC 2009: 358-359 - 2006
- [c2]Akira Tanabe, Ken'ichiro Hijioka, Yoshihiro Hayashi:
A Novel Monitoring Method of RF Characteristics Variations for Sub-0.1μm MOSFETs with Precise Gate-resistance Model. CICC 2006: 725-728 - 2003
- [j4]Akira Tanabe, Yasushi Nakahara, Akio Furukawa, Tohru Mogami:
A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC. IEEE J. Solid State Circuits 38(1): 107-113 (2003) - 2001
- [j3]Akira Tanabe, Masato Umetani, Ikuo Fujiwara, Takayuki Ogura, Kotaro Kataoka, Masao Okihara, Hiroshi Sakuraba, Tetsuo Endoh, Fujio Masuoka:
0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation. IEEE J. Solid State Circuits 36(6): 988-996 (2001) - [c1]Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori:
Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. ASP-DAC 2001: 267-268
1990 – 1999
- 1998
- [j2]Akira Tanabe, Masaaki Soda, Yasushi Nakahara, Takao Tamura, Kazuyoshi Yoshida, Akio Furukawa:
A single-chip 2.4-Gb/s CMOS optical receiver IC with low substrate cross-talk preamplifier. IEEE J. Solid State Circuits 33(12): 2148-2153 (1998) - 1996
- [j1]Masakazu Kurisu, Makoto Kaneko, Tetsuyuki Suzaki, Akira Tanabe, Mitsuhiro Togo, Akio Furukawa, Takao Tamura, Ken Nakajima, Kazuyoshi Yoshida:
2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8: 1 multiplexers with a 0.15-μm CMOS technology. IEEE J. Solid State Circuits 31(12): 2024-2029 (1996)
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