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Yatish Patel
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2010 – 2019
- 2010
- [b1]Yatish Patel:
Communication and Control for Quantum Circuits. University of California, Berkeley, USA, 2010
2000 – 2009
- 2009
- [c8]Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz:
A fault tolerant, area efficient architecture for Shor's factoring algorithm. ISCA 2009: 383-394 - [c7]Yury Markovsky, Yatish Patel, John Wawrzynek:
Using adaptive routing to compensate for performance heterogeneity. NOCS 2009: 12-21 - 2008
- [c6]Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz:
Running a Quantum Circuit at the Speed of Data. ISCA 2008: 177-188 - 2007
- [c5]Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz:
Automated generation of layout and control for quantum circuits. Conf. Computing Frontiers 2007: 83-94 - 2006
- [c4]Nemanja Isailovic, Yatish Patel, Mark Whitney, John Kubiatowicz:
Interconnection Networks for Scalable Quantum Computers. ISCA 2006: 366-377 - 2004
- [j1]Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz, Dean Copsey, Frederic T. Chong
, Isaac L. Chuang, Mark Oskin:
Datapath and control for quantum wires. ACM Trans. Archit. Code Optim. 1(1): 34-61 (2004) - [c3]Victor Wen, Mark Whitney, Yatish Patel, John Kubiatowicz:
Exploiting Prediction to Reduce Power on Buses. HPCA 2004: 2-13 - 2003
- [c2]Nicholas Weaver, Yury Markovsky, Yatish Patel, John Wawrzynek:
Post-placement C-slow retiming for the xilinx virtex FPGA. FPGA 2003: 185-194 - 2002
- [c1]Massimo Baleani, Frank Gennari, Yunjian Jiang, Yatish Patel, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform. CODES 2002: 151-156
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